Re: x86 PCU

Mindaugas Rasiukevicius <[email protected]>
Newsgroups gmane.os.netbsd.ports.x86-64,gmane.os.netbsd.ports.i386
Message-ID <[email protected]>
Thor Lancelot Simon <[email protected]> wrote:
> About 3 years ago Matthias Drochner committed changes to use the MI pcu
> framework for lazy FPU switch on x86.
> 
> This was quickly backed out by Christos because, evidently, it caused
> system hangs.
> 
> I am implementing AESNI support as well as some other code that wants
> "FPU" registers in the kernel, and I am cringing every time I type in
> code that manually saves and restores the FPU state at a cost of hundreds
> of cycles per.  So I would love to see PCU working on x86.
> 
> I can't find much discussion of what was wrong -- aside from the commit
> message when the code was backed out, saying it had caused hangs.  Does
> anyone remember or know more about this?  Would anyone be willing to have
> another shot at making it go?
> 

There were some lockups which we never properly debugged.  It seemed
to be related to the fact that PCU used xcall(9) powered by software
interrupts to coordinate coherency between CPUs.  At some point later
I implemented MI ipi(9) interface and converted pcu(9) to use IPIs
instead of softints (IPIs have way much lower overhead).  Conversion
to IPIs may or may not have fixed the lockups.

For the in-kernel use of PCU, as discussed elsewhere, we should add
the pcu_crit_enter()/pcu_crit_exit() primitives and have much simpler
mechanism (compared to the in-kernel lazy switching which was just
too complex).

-- 
Mindaugas
lmpx.com only provides a reader for public news (NNTP) servers. It is not affiliated with the servers or forums shown here and is not responsible for the content of articles, which is written by their respective authors.