Re: x86 bus_dmamap_sync
Robert Elz <[email protected]>
| Newsgroups | gmane.os.netbsd.ports.x86-64,gmane.os.netbsd.ports.i386 |
|---|---|
| Message-ID | <[email protected]> |
Date: Sat, 28 Oct 2017 21:26:18 +0200
From: Manuel Bouyer <[email protected]>
Message-ID: <[email protected]>
| But I'm not sure that without *fence insctructions, two writes to the
| same location (or close locations) will be seen as two writes on the memory
| side.
Just restating what you're writing (as I don't know x86 hardware, or for that
matter, any modern hardware, at all) ...
But might the issue be successive writes to the same location - I can imagine
that some "smart" processor, without some kind of barrier inserted bwtewwn,
might optimise out the first one as being useless - which in regular RAM it
would be, but not when the destination is a device register.
kre