legacy interrupts on pci interrupt establish path.
Cherry G.Mathew <[email protected]>
| Newsgroups | gmane.os.netbsd.ports.xen,gmane.os.netbsd.ports.x86-64,gmane.os.netbsd.ports.i386 |
|---|---|
| Message-ID | <[email protected]> |
Hello,
I'd like to propose the following diff:
diff -r e8efcad62fc7 -r deb181d94ab1 sys/arch/x86/pci/pci_intr_machdep.c
--- a/sys/arch/x86/pci/pci_intr_machdep.c Wed Aug 22 14:12:30 2018 +0000
+++ b/sys/arch/x86/pci/pci_intr_machdep.c Wed Aug 29 07:40:56 2018 +0000
@@ -294,9 +294,7 @@
return ENOENT;
*pic = &ioapic->sc_pic;
*pin = APIC_IRQ_PIN(ih);
- *irq = APIC_IRQ_LEGACY_IRQ(ih);
- if (*irq < 0 || *irq >= NUM_LEGACY_IRQS)
- *irq = -1;
+ *irq = -1; /* PCI doesn't use legacy irq */
}
#endif
afaiu, legacy irq is only relevant to the isa_interrupt_establish..()
path or when IOAPIC support is disabled in the kernel.
With PCI and -D NIOAPIC support, the {ioapic, pin} tuple are
reprogrammed onto specific lapic vectors and any boot time/ BIOS
legacy irq mappings are thus overridden.
I'm open to revising my understanding of this.
Patches have been tested on native by gson@
http://www.gson.org/netbsd/bugs/build/i386-cherry/2018/2018.08.27.16.30.51/test.log
http://www.gson.org/netbsd/bugs/build/amd64-cherry/2018/2018.08.27.16.30.51/test.log
This will also help with a separate unifying XEN related patch.
Please let me know if you have any objections to committing this.
--
~cherry