Re: 10.0 DMA Issues With SIS-5597/5598 Chipset
"J. Alexander Jacocks" <[email protected]> Tue, 18 Jun 2024 12:27:45 -0400
| Newsgroups | gmane.os.netbsd.general,gmane.os.netbsd.ports.i386 |
|---|---|
| Message-ID | <CAF-r0Y1282Acvf3ahU1qD03j4vF-t4tHZK9RjgWaKUS96zLvVA@mail.gmail.com> |
--000000000000514ff0061b2c90ef Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Thu, Jun 13, 2024 at 2:59=E2=80=AFPM J. Alexander Jacocks <jjacocks@mac.= com> wrote: > On Thu, Jun 13, 2024 at 2:55=E2=80=AFPM Alexander Jacocks <jjacocks@gmail= .com> > wrote: > >> On Thu, Jun 13, 2024 at 10:04=E2=80=AFAM Manuel Bouyer <bouyer@antioche.= eu.org> >> wrote: >> >>> On Thu, Jun 13, 2024 at 09:58:34AM -0400, Alexander Jacocks wrote: >>> > >>> > > On Jun 13, 2024, at 8:44?AM, Manuel Bouyer <[email protected]> >>> wrote: >>> > > >>> > > ?On Thu, Jun 13, 2024 at 08:39:37AM -0400, Alexander Jacocks wrote: >>> > >> >>> > >>>> On Jun 13, 2024, at 5:51?AM, Manuel Bouyer < >>> [email protected]> wrote: >>> > >>> >>> > >>> ?On Wed, Jun 12, 2024 at 10:29:59AM -0400, Alexander Jacocks wrot= e: >>> > >>>> And it was pointed out to me that my paste of the DMA error was >>> incorrect. >>> > >>>> Here is the correct log: >>> > >>>> [ 1.000004] pci0 at mainbus0 bus 0: configuration mode 1 >>> > >>>> [ 1.000004] pci0: i/o space, memory space enabled, rd/line, >>> rd/mult, >>> > >>>> wr/inv ok >>> > >>>> [ 1.000004] pchb0 at pci0 dev 0 function 0: Silicon >>> Integrated System >>> > >>>> 5597/5598 Host Bridge (rev. 0x10) >>> > >>>> [ 1.000004] pcib0 at pci0 dev 1 function 0: Silicon >>> Integrated System >>> > >>>> 85C503 or 5597/5598 ISA Bridge (rev. 0x01) >>> > >>>> [ 1.000004] siside0 at pci0 dev 1 function 1 >>> > >>>> [ 1.000004] siside0: Silicon Integrated Systems 5597/5598 I= DE >>> > >>>> controller (rev. 0xd0) >>> > >>>> [ 1.000004] siside0: bus-master DMA support present, but >>> unused >>> > >>>> (couldn't map registers) >>> > >>> >>> > >>> The problem here is that the DMA registers are not mappable, so >>> can't be >>> > >>> used by the driver. Some BIOS settings (like PnP support) may >>> affect this. >>> > >>> >>> > >>>> [ 1.000004] siside0: secondary channel ignored (disabled) >>> > >>>> I tried simply forcing DMA on by adding the 0x0001 flag to the >>> pciide >>> > >>>> driver, with a minor mod to the GENERIC kernel, but it didn't >>> change the >>> > >>>> behavior any. I also attempted to add in a Maxtor SATA-150 PCI >>> IDE >>> > >>> >>> > >>> Yes, that won't work in this case. >>> > >> >>> > >> Interesting. I was able to verify that Windows 98SE is able to >>> enable DMA support, even with the current BIOS settings. This BIOS is >>> pretty limited in what can be configured, unfortunately. >>> > > >>> > > From memory, win98 was the "PnP OS". it had to be disabled for >>> others. >>> > > >>> > >> >>> > >> Would disabling ACPI and enabling APM possibly help? Since this >>> board clearly has a broken ACPI configuration, that seems like a >>> possibility. >>> > > >>> > > No APM is something different >>> > > >>> > >>> > And PNP is currently disabled, as much as is possible. Is there >>> anything else that I can try to do to make the registers mappable? >>> >>> Can you send the output of a pcictl dump for this device ? >> >> >> Manuel, >> >> Here are the PCI devices in the system: >> >> 586ve$ sudo pcictl pci0 list -N >> 000:00:0: Silicon Integrated System 5597/5598 Host Bridge (host bridge, >> revision 0x10) [pchb0] >> 000:01:0: Silicon Integrated System 85C503 or 5597/5598 ISA Bridge (ISA >> bridge, revision 0x01) [pcib0] >> 000:01:1: Silicon Integrated System 5597/5598 IDE Controller (IDE mass >> storage, interface 0x8a, revision 0xd0) [siside0] >> 000:01:2: Silicon Integrated System 5597/5598 USB Host Controller (USB >> serial bus, OHCI, revision 0x10) [ohci0] >> 000:02:0: Silicon Integrated System 900 10/100 Ethernet (ethernet >> network, revision 0x02) [sip0] >> 000:08:0: Silicon Integrated System 5597/5598 Integrated VGA (VGA >> display, revision 0x68) [vga0] >> >> And here is the dump: >> >> 586ve$ pcictl pci0 list| awk -F: '{print "pcictl pci0 dump -b "$1" -d >> "$2}'|sort -u | sh >> PCI configuration registers: >> Common header: >> 0x00: 0x55971039 0x22000007 0x06000010 0x00001000 >> >> Vendor Name: Silicon Integrated System (0x1039) >> Device Name: 5597/5598 Host Bridge (0x5597) >> Command register: 0x0007 >> I/O space accesses: on >> Memory space accesses: on >> Bus mastering: on >> Special cycles: off >> MWI transactions: off >> Palette snooping: off >> Parity error checking: off >> Address/data stepping: off >> System error (SERR): off >> Fast back-to-back transactions: off >> Interrupt disable: off >> Status register: 0x2200 >> Immediate Readiness: off >> Interrupt status: inactive >> Capability List support: off >> 66 MHz capable: off >> User Definable Features (UDF) support: off >> Fast back-to-back capable: off >> Data parity error detected: off >> DEVSEL timing: medium (0x1) >> Slave signaled Target Abort: off >> Master received Target Abort: off >> Master received Master Abort: on >> Asserted System Error (SERR): off >> Parity error detected: off >> Class Name: bridge (0x06) >> Subclass Name: host (0x00) >> Interface: 0x00 >> Revision ID: 0x10 >> BIST: 0x00 >> Header Type: 0x00 (0x00) >> Latency Timer: 0x10 >> Cache Line Size: 0bytes (0x00) >> >> Type 0 ("normal" device) header: >> 0x10: 0x00000000 0x00000000 0x00000000 0x00000000 >> 0x20: 0x00000000 0x00000000 0x00000000 0x00000000 >> 0x30: 0x00000000 0x00000000 0x00000000 0x00000000 >> >> Base address register at 0x10 >> not implemented >> Base address register at 0x14 >> not implemented >> Base address register at 0x18 >> not implemented >> Base address register at 0x1c >> not implemented >> Base address register at 0x20 >> not implemented >> Base address register at 0x24 >> not implemented >> Cardbus CIS Pointer: 0x00000000 >> Subsystem vendor ID: 0x0000 >> Subsystem ID: 0x0000 >> Expansion ROM Base Address Register: 0x00000000 >> base: 0x00000000 >> Expansion ROM Enable: off >> Validation Status: Validation not supported >> Validation Details: 0x0 >> Reserved @ 0x34: 0x00000000 >> Reserved @ 0x38: 0x00000000 >> Maximum Latency: 0x00 >> Minimum Grant: 0x00 >> Interrupt pin: 0x00 (none) >> Interrupt line: 0x00 >> >> Device-dependent header: >> 0x40: 0x00000000 0x00000000 0x00000000 0x00000000 >> 0x50: 0x1e70eac0 0x11a32a01 0x0003ff08 0x00000000 >> 0x60: 0x0303e6ea 0xff00ff00 0xff00ff00 0x782000c0 >> 0x70: 0x00008088 0x00808888 0x00000000 0x00000000 >> 0x80: 0xffcec458 0x40100040 0xffff0000 0x00000000 >> 0x90: 0x00000002 0x00000000 0x00000000 0xffff0000 >> 0xa0: 0x80ffffff 0x00000000 0x00000000 0x00000000 >> 0xb0: 0x00000000 0x00000000 0x00000000 0x00000000 >> 0xc0: 0x00000000 0x00000000 0x00000000 0x00000000 >> 0xd0: 0x00000000 0x00000000 0x00000000 0x00000000 >> 0xe0: 0x00000000 0x00000000 0x00000000 0x00000000 >> 0xf0: 0x00000000 0x00000000 0x00000000 0x00000000 >> PCI configuration registers: >> Common header: >> 0x00: 0x00081039 0x02000007 0x06010001 0x00800000 >> >> Vendor Name: Silicon Integrated System (0x1039) >> Device Name: 85C503 or 5597/5598 ISA Bridge (0x0008) >> Command register: 0x0007 >> I/O space accesses: on >> Memory space accesses: on >> Bus mastering: on >> Special cycles: off >> MWI transactions: off >> Palette snooping: off >> Parity error checking: off >> Address/data stepping: off >> System error (SERR): off >> Fast back-to-back transactions: off >> Interrupt disable: off >> Status register: 0x0200 >> Immediate Readiness: off >> Interrupt status: inactive >> Capability List support: off >> 66 MHz capable: off >> User Definable Features (UDF) support: off >> Fast back-to-back capable: off >> Data parity error detected: off >> DEVSEL timing: medium (0x1) >> Slave signaled Target Abort: off >> Master received Target Abort: off >> Master received Master Abort: off >> Asserted System Error (SERR): off >> Parity error detected: off >> Class Name: bridge (0x06) >> Subclass Name: ISA (0x01) >> Interface: 0x00 >> Revision ID: 0x01 >> BIST: 0x00 >> Header Type: 0x00+multifunction (0x80) >> Latency Timer: 0x00 >> Cache Line Size: 0bytes (0x00) >> >> Type 0 ("normal" device) header: >> 0x10: 0x00000000 0x00000000 0x00000000 0x00000000 >> 0x20: 0x00000000 0x00000000 0x00000000 0x00000000 >> 0x30: 0x00000000 0x00000000 0x00000000 0x00000000 >> >> Base address register at 0x10 >> not implemented >> Base address register at 0x14 >> not implemented >> Base address register at 0x18 >> not implemented >> Base address register at 0x1c >> not implemented >> Base address register at 0x20 >> not implemented >> Base address register at 0x24 >> not implemented >> Cardbus CIS Pointer: 0x00000000 >> Subsystem vendor ID: 0x0000 >> Subsystem ID: 0x0000 >> Expansion ROM Base Address Register: 0x00000000 >> base: 0x00000000 >> Expansion ROM Enable: off >> Validation Status: Validation not supported >> Validation Details: 0x0 >> Reserved @ 0x34: 0x00000000 >> Reserved @ 0x38: 0x00000000 >> Maximum Latency: 0x00 >> Minimum Grant: 0x00 >> Interrupt pin: 0x00 (none) >> Interrupt line: 0x00 >> >> Device-dependent header: >> 0x40: 0x0b800ffa 0x06006480 0x0f1000ff 0x01042011 >> 0x50: 0x01022811 0x0a670a62 0x00122e9c 0x000004a8 >> 0x60: 0x004f8032 0x80015b00 0x00120000 0x00001c20 >> 0x70: 0x0000001e 0xa325a321 0x00000000 0x00000000 >> 0x80: 0x00000000 0x00000000 0x00000000 0x00000000 >> 0x90: 0x00003f00 0x00000000 0x00000000 0x00000000 >> 0xa0: 0x00000000 0x00000000 0x00000000 0x00000000 >> 0xb0: 0x00000000 0x00000000 0x00000000 0x00000000 >> 0xc0: 0x00000000 0x00000000 0x00000000 0x00000000 >> 0xd0: 0x00000000 0x00000000 0x00000000 0x00000000 >> 0xe0: 0x00000000 0x00000000 0x00000000 0x00000000 >> 0xf0: 0x00000000 0x00000000 0x00000000 0x00000000 >> PCI configuration registers: >> Common header: >> 0x00: 0x09001039 0x02900107 0x02000002 0x0000d000 >> >> Vendor Name: Silicon Integrated System (0x1039) >> Device Name: 900 10/100 Ethernet (0x0900) >> Command register: 0x0107 >> I/O space accesses: on >> Memory space accesses: on >> Bus mastering: on >> Special cycles: off >> MWI transactions: off >> Palette snooping: off >> Parity error checking: off >> Address/data stepping: off >> System error (SERR): on >> Fast back-to-back transactions: off >> Interrupt disable: off >> Status register: 0x0290 >> Immediate Readiness: off >> Interrupt status: inactive >> Capability List support: on >> 66 MHz capable: off >> User Definable Features (UDF) support: off >> Fast back-to-back capable: on >> Data parity error detected: off >> DEVSEL timing: medium (0x1) >> Slave signaled Target Abort: off >> Master received Target Abort: off >> Master received Master Abort: off >> Asserted System Error (SERR): off >> Parity error detected: off >> Class Name: network (0x02) >> Subclass Name: ethernet (0x00) >> Interface: 0x00 >> Revision ID: 0x02 >> BIST: 0x00 >> Header Type: 0x00 (0x00) >> Latency Timer: 0xd0 >> Cache Line Size: 0bytes (0x00) >> >> Type 0 ("normal" device) header: >> 0x10: 0x00004001 0x60000000 0x00000000 0x00000000 >> 0x20: 0x00000000 0x00000000 0x00000000 0x09001039 >> 0x30: 0x00000000 0x00000040 0x00000000 0x0b34010f >> >> Base address register at 0x10 >> type: I/O >> base: 0x00004000 >> Base address register at 0x14 >> type: 32-bit nonprefetchable memory >> base: 0x60000000 >> Base address register at 0x18 >> not implemented >> Base address register at 0x1c >> not implemented >> Base address register at 0x20 >> not implemented >> Base address register at 0x24 >> not implemented >> Cardbus CIS Pointer: 0x00000000 >> Subsystem vendor ID: 0x1039 >> Subsystem ID: 0x0900 >> Expansion ROM Base Address Register: 0x00000000 >> base: 0x00000000 >> Expansion ROM Enable: off >> Validation Status: Validation not supported >> Validation Details: 0x0 >> Capability list pointer: 0x40 >> Reserved @ 0x38: 0x00000000 >> Maximum Latency: 0x0b >> Minimum Grant: 0x34 >> Interrupt pin: 0x01 (pin A) >> Interrupt line: 0x0f >> >> Capability register at 0x40 >> type: 0x01 (Power Management) >> >> PCI Power Management Capabilities Register >> Capabilities register: 0xfe01 >> Version: 1.0 >> PME# clock: off >> Device specific initialization: off >> 3.3V auxiliary current: self-powered >> D1 power management state support: on >> D2 power management state support: on >> PME# support D0: on >> PME# support D1: on >> PME# support D2: on >> PME# support D3 hot: on >> PME# support D3 cold: on >> Control/status register: 0x00000000 >> Power state: D0 >> PCI Express reserved: off >> No soft reset: off >> PME# assertion: disabled >> Data Select: 0 >> Data Scale: 0 >> PME# status: off >> Bridge Support Extensions register: 0x00 >> B2/B3 support: off >> Bus Power/Clock Control Enable: off >> Data register: 0x00 >> >> Device-dependent header: >> 0x40: 0xfe010001 0x00000000 0x00000000 0x00000000 >> 0x50: 0x00000000 0x00000000 0x00000000 0x00000000 >> 0x60: 0x00000000 0x00000000 0x00000000 0x00000000 >> 0x70: 0x00000000 0x00000000 0x00000000 0x00000000 >> 0x80: 0x00000000 0x00000000 0x00000000 0x00000000 >> 0x90: 0x00000000 0x00000000 0x00000000 0x00000000 >> 0xa0: 0x00000000 0x00000000 0x00000000 0x00000000 >> 0xb0: 0x00000000 0x00000000 0x00000000 0x00000000 >> 0xc0: 0x00000000 0x00000000 0x00000000 0x00000000 >> 0xd0: 0x00000000 0x00000000 0x00000000 0x00000000 >> 0xe0: 0x00000000 0x00000000 0x00000000 0x00000000 >> 0xf0: 0x00000000 0x00000000 0x00000000 0x00000000 >> pcictl: "08" is not a number >> > > And here is the IDE controller: > > 586ve$ pcictl pci0 dump -b 000 -d 01 -f 1 > PCI configuration registers: > Common header: > 0x00: 0x55131039 0x00000001 0x01018ad0 0x00800000 > > Vendor Name: Silicon Integrated System (0x1039) > Device Name: 5597/5598 IDE Controller (0x5513) > Command register: 0x0001 > I/O space accesses: on > Memory space accesses: off > Bus mastering: off > Special cycles: off > MWI transactions: off > Palette snooping: off > Parity error checking: off > Address/data stepping: off > System error (SERR): off > Fast back-to-back transactions: off > Interrupt disable: off > Status register: 0x0000 > Immediate Readiness: off > Interrupt status: inactive > Capability List support: off > 66 MHz capable: off > User Definable Features (UDF) support: off > Fast back-to-back capable: off > Data parity error detected: off > DEVSEL timing: fast (0x0) > Slave signaled Target Abort: off > Master received Target Abort: off > Master received Master Abort: off > Asserted System Error (SERR): off > Parity error detected: off > Class Name: mass storage (0x01) > Subclass Name: IDE (0x01) > Interface: 0x8a > Revision ID: 0xd0 > BIST: 0x00 > Header Type: 0x00+multifunction (0x80) > Latency Timer: 0x00 > Cache Line Size: 0bytes (0x00) > > Type 0 ("normal" device) header: > 0x10: 0x00002001 0x00002101 0x00002201 0x00002301 > 0x20: 0xfd64ffa1 0x00000000 0x00000000 0x1d97af69 > 0x30: 0x00000000 0x00000000 0x00000000 0x00000100 > > Base address register at 0x10 > type: I/O > base: 0x00002000 > Base address register at 0x14 > type: I/O > base: 0x00002100 > Base address register at 0x18 > type: I/O > base: 0x00002200 > Base address register at 0x1c > type: I/O > base: 0x00002300 > Base address register at 0x20 > type: I/O > base: 0xfd64ffa0 > Base address register at 0x24 > not implemented > Cardbus CIS Pointer: 0x00000000 > Subsystem vendor ID: 0xaf69 > Subsystem ID: 0x1d97 > Expansion ROM Base Address Register: 0x00000000 > base: 0x00000000 > Expansion ROM Enable: off > Validation Status: Validation not supported > Validation Details: 0x0 > Reserved @ 0x34: 0x00000000 > Reserved @ 0x38: 0x00000000 > Maximum Latency: 0x00 > Minimum Grant: 0x00 > Interrupt pin: 0x01 (pin A) > Interrupt line: 0x00 > > Device-dependent header: > 0x40: 0x00000301 0x00000000 0x03220700 0x02000200 > 0x50: 0x000d0200 0x00000000 0x00000000 0x00000000 > 0x60: 0x00000000 0x00000000 0x00000000 0x00000000 > 0x70: 0x00000000 0x00000000 0x00000000 0x00000000 > 0x80: 0x00000000 0x00000000 0x00000000 0x00000000 > 0x90: 0x00000000 0x00000000 0x00000000 0x00000000 > 0xa0: 0x00000000 0x00000000 0x00000000 0x00000000 > 0xb0: 0x00000000 0x00000000 0x00000000 0x00000000 > 0xc0: 0x00000000 0x00000000 0x00000000 0x00000000 > 0xd0: 0x00000000 0x00000000 0x00000000 0x00000000 > 0xe0: 0x00000000 0x00000000 0x00000000 0x00000000 > 0xf0: 0x00000000 0x00000000 0x00000000 0x00000000 > > - Alex > Did this reveal any clues to the source of the problem? Thanks! - Alex --000000000000514ff0061b2c90ef Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable <div dir=3D"ltr"><div dir=3D"ltr"></div><br><div class=3D"gmail_quote"><div= dir=3D"ltr" class=3D"gmail_attr">On Thu, Jun 13, 2024 at 2:59=E2=80=AFPM J= . Alexander Jacocks <<a href=3D"mailto:[email protected]">[email protected]= m</a>> wrote:<br></div><blockquote class=3D"gmail_quote" style=3D"margin= :0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"= ><div dir=3D"ltr"><div class=3D"gmail_quote"><div dir=3D"ltr" class=3D"gmai= l_attr">On Thu, Jun 13, 2024 at 2:55=E2=80=AFPM Alexander Jacocks <<a hr= ef=3D"mailto:[email protected]" target=3D"_blank">[email protected]</a>&g= t; wrote:<br></div><blockquote class=3D"gmail_quote" style=3D"margin:0px 0p= x 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><div d= ir=3D"ltr"><div dir=3D"ltr"></div><div class=3D"gmail_quote"><div dir=3D"lt= r" class=3D"gmail_attr">On Thu, Jun 13, 2024 at 10:04=E2=80=AFAM Manuel Bou= yer <<a href=3D"mailto:[email protected]" target=3D"_blank">bouyer@= antioche.eu.org</a>> wrote:<br></div><blockquote class=3D"gmail_quote" s= tyle=3D"margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);pad= ding-left:1ex">On Thu, Jun 13, 2024 at 09:58:34AM -0400, Alexander Jacocks = wrote:<br> > <br> > > On Jun 13, 2024, at 8:44?AM, Manuel Bouyer <<a href=3D"mailto:= [email protected]" target=3D"_blank">[email protected]</a>> wr= ote:<br> > > <br> > > ?On Thu, Jun 13, 2024 at 08:39:37AM -0400, Alexander Jacocks wrot= e:<br> > >> <br> > >>>> On Jun 13, 2024, at 5:51?AM, Manuel Bouyer <<a hre= f=3D"mailto:[email protected]" target=3D"_blank">[email protected]= g</a>> wrote:<br> > >>> <br> > >>> ?On Wed, Jun 12, 2024 at 10:29:59AM -0400, Alexander Jaco= cks wrote:<br> > >>>>=C2=A0 And it was pointed out to me that my paste of t= he DMA error was incorrect.<br> > >>>>=C2=A0 Here is the correct log:<br> > >>>>=C2=A0 [=C2=A0 =C2=A0 =C2=A01.000004] pci0 at mainbus0= bus 0: configuration mode 1<br> > >>>>=C2=A0 [=C2=A0 =C2=A0 =C2=A01.000004] pci0: i/o space,= memory space enabled, rd/line, rd/mult,<br> > >>>>=C2=A0 wr/inv ok<br> > >>>>=C2=A0 [=C2=A0 =C2=A0 =C2=A01.000004] pchb0 at pci0 de= v 0 function 0: Silicon Integrated System<br> > >>>>=C2=A0 5597/5598 Host Bridge (rev. 0x10)<br> > >>>>=C2=A0 [=C2=A0 =C2=A0 =C2=A01.000004] pcib0 at pci0 de= v 1 function 0: Silicon Integrated System<br> > >>>>=C2=A0 85C503 or 5597/5598 ISA Bridge (rev. 0x01)<br> > >>>>=C2=A0 [=C2=A0 =C2=A0 =C2=A01.000004] siside0 at pci0 = dev 1 function 1<br> > >>>>=C2=A0 [=C2=A0 =C2=A0 =C2=A01.000004] siside0: Silicon= Integrated Systems 5597/5598 IDE<br> > >>>>=C2=A0 controller (rev. 0xd0)<br> > >>>>=C2=A0 [=C2=A0 =C2=A0 =C2=A01.000004] siside0: bus-mas= ter DMA support present, but unused<br> > >>>>=C2=A0 (couldn't map registers)<br> > >>> <br> > >>> The problem here is that the DMA registers are not mappab= le, so can't be<br> > >>> used by the driver. Some BIOS settings (like PnP support)= may affect this.<br> > >>> <br> > >>>>=C2=A0 [=C2=A0 =C2=A0 =C2=A01.000004] siside0: seconda= ry channel ignored (disabled)<br> > >>>>=C2=A0 I tried simply forcing DMA on by adding the 0x0= 001 flag to the pciide<br> > >>>>=C2=A0 driver, with a minor mod to the GENERIC kernel,= but it didn't change the<br> > >>>>=C2=A0 behavior any. I also attempted to add in a Maxt= or SATA-150 PCI IDE<br> > >>> <br> > >>> Yes, that won't work in this case.<br> > >> <br> > >> Interesting. I was able to verify that Windows 98SE is able t= o enable DMA support, even with the current BIOS settings. This BIOS is pre= tty limited in what can be configured, unfortunately.<br> > > <br> > > From memory, win98 was the "PnP OS". it had to be disab= led for others.<br> > > <br> > >> <br> > >> Would disabling ACPI and enabling APM possibly help? Since th= is board clearly has a broken ACPI configuration, that seems like a possibi= lity.<br> > > <br> > > No APM is something different<br> > > <br> > <br> > And PNP is currently disabled, as much as is possible. Is there anythi= ng else that I can try to do to make the registers mappable?<br> <br> Can you send the output of a pcictl dump for this device ?</blockquote><div= ><br></div><div>Manuel,</div><div><br></div><div>Here are the PCI devices i= n the system:</div><div><br></div><div>586ve$ sudo pcictl pci0 list -N<br>0= 00:00:0: Silicon Integrated System 5597/5598 Host Bridge (host bridge, revi= sion 0x10) [pchb0]<br>000:01:0: Silicon Integrated System 85C503 or 5597/55= 98 ISA Bridge (ISA bridge, revision 0x01) [pcib0]<br>000:01:1: Silicon Inte= grated System 5597/5598 IDE Controller (IDE mass storage, interface 0x8a, r= evision 0xd0) [siside0]<br>000:01:2: Silicon Integrated System 5597/5598 US= B Host Controller (USB serial bus, OHCI, revision 0x10) [ohci0]<br>000:02:0= : Silicon Integrated System 900 10/100 Ethernet (ethernet network, revision= 0x02) [sip0]<br>000:08:0: Silicon Integrated System 5597/5598 Integrated V= GA (VGA display, revision 0x68) [vga0]</div><div><br></div><div>And here is= the dump:<br><br>586ve$ pcictl pci0 list| awk -F: '{print "pcictl= pci0 dump -b "$1" -d "$2}'|sort -u | sh<br>PCI configur= ation registers:<br>=C2=A0 Common header:<br>=C2=A0 =C2=A0 0x00: 0x55971039= 0x22000007 0x06000010 0x00001000<br><br>=C2=A0 =C2=A0 Vendor Name: Silicon= Integrated System (0x1039)<br>=C2=A0 =C2=A0 Device Name: 5597/5598 Host Br= idge (0x5597)<br>=C2=A0 =C2=A0 Command register: 0x0007<br>=C2=A0 =C2=A0 = =C2=A0 I/O space accesses: on<br>=C2=A0 =C2=A0 =C2=A0 Memory space accesses= : on<br>=C2=A0 =C2=A0 =C2=A0 Bus mastering: on<br>=C2=A0 =C2=A0 =C2=A0 Spec= ial cycles: off<br>=C2=A0 =C2=A0 =C2=A0 MWI transactions: off<br>=C2=A0 =C2= =A0 =C2=A0 Palette snooping: off<br>=C2=A0 =C2=A0 =C2=A0 Parity error check= ing: off<br>=C2=A0 =C2=A0 =C2=A0 Address/data stepping: off<br>=C2=A0 =C2= =A0 =C2=A0 System error (SERR): off<br>=C2=A0 =C2=A0 =C2=A0 Fast back-to-ba= ck transactions: off<br>=C2=A0 =C2=A0 =C2=A0 Interrupt disable: off<br>=C2= =A0 =C2=A0 Status register: 0x2200<br>=C2=A0 =C2=A0 =C2=A0 Immediate Readin= ess: off<br>=C2=A0 =C2=A0 =C2=A0 Interrupt status: inactive<br>=C2=A0 =C2= =A0 =C2=A0 Capability List support: off<br>=C2=A0 =C2=A0 =C2=A0 66 MHz capa= ble: off<br>=C2=A0 =C2=A0 =C2=A0 User Definable Features (UDF) support: off= <br>=C2=A0 =C2=A0 =C2=A0 Fast back-to-back capable: off<br>=C2=A0 =C2=A0 = =C2=A0 Data parity error detected: off<br>=C2=A0 =C2=A0 =C2=A0 DEVSEL timin= g: medium (0x1)<br>=C2=A0 =C2=A0 =C2=A0 Slave signaled Target Abort: off<br= >=C2=A0 =C2=A0 =C2=A0 Master received Target Abort: off<br>=C2=A0 =C2=A0 = =C2=A0 Master received Master Abort: on<br>=C2=A0 =C2=A0 =C2=A0 Asserted Sy= stem Error (SERR): off<br>=C2=A0 =C2=A0 =C2=A0 Parity error detected: off<b= r>=C2=A0 =C2=A0 Class Name: bridge (0x06)<br>=C2=A0 =C2=A0 Subclass Name: h= ost (0x00)<br>=C2=A0 =C2=A0 Interface: 0x00<br>=C2=A0 =C2=A0 Revision ID: 0= x10<br>=C2=A0 =C2=A0 BIST: 0x00<br>=C2=A0 =C2=A0 Header Type: 0x00 (0x00)<b= r>=C2=A0 =C2=A0 Latency Timer: 0x10<br>=C2=A0 =C2=A0 Cache Line Size: 0byte= s (0x00)<br><br>=C2=A0 Type 0 ("normal" device) header:<br>=C2=A0= =C2=A0 0x10: 0x00000000 0x00000000 0x00000000 0x00000000<br>=C2=A0 =C2=A0 = 0x20: 0x00000000 0x00000000 0x00000000 0x00000000<br>=C2=A0 =C2=A0 0x30: 0x= 00000000 0x00000000 0x00000000 0x00000000<br><br>=C2=A0 =C2=A0 Base address= register at 0x10<br>=C2=A0 =C2=A0 =C2=A0 not implemented<br>=C2=A0 =C2=A0 = Base address register at 0x14<br>=C2=A0 =C2=A0 =C2=A0 not implemented<br>= =C2=A0 =C2=A0 Base address register at 0x18<br>=C2=A0 =C2=A0 =C2=A0 not imp= lemented<br>=C2=A0 =C2=A0 Base address register at 0x1c<br>=C2=A0 =C2=A0 = =C2=A0 not implemented<br>=C2=A0 =C2=A0 Base address register at 0x20<br>= =C2=A0 =C2=A0 =C2=A0 not implemented<br>=C2=A0 =C2=A0 Base address register= at 0x24<br>=C2=A0 =C2=A0 =C2=A0 not implemented<br>=C2=A0 =C2=A0 Cardbus C= IS Pointer: 0x00000000<br>=C2=A0 =C2=A0 Subsystem vendor ID: 0x0000<br>=C2= =A0 =C2=A0 Subsystem ID: 0x0000<br>=C2=A0 =C2=A0 Expansion ROM Base Address= Register: 0x00000000<br>=C2=A0 =C2=A0 =C2=A0 base: 0x00000000<br>=C2=A0 = =C2=A0 =C2=A0 Expansion ROM Enable: off<br>=C2=A0 =C2=A0 =C2=A0 Validation = Status: Validation not supported<br>=C2=A0 =C2=A0 =C2=A0 Validation Details= : 0x0<br>=C2=A0 =C2=A0 Reserved @ 0x34: 0x00000000<br>=C2=A0 =C2=A0 Reserve= d @ 0x38: 0x00000000<br>=C2=A0 =C2=A0 Maximum Latency: 0x00<br>=C2=A0 =C2= =A0 Minimum Grant: 0x00<br>=C2=A0 =C2=A0 Interrupt pin: 0x00 (none)<br>=C2= =A0 =C2=A0 Interrupt line: 0x00<br><br>=C2=A0 Device-dependent header:<br>= =C2=A0 =C2=A0 0x40: 0x00000000 0x00000000 0x00000000 0x00000000<br>=C2=A0 = =C2=A0 0x50: 0x1e70eac0 0x11a32a01 0x0003ff08 0x00000000<br>=C2=A0 =C2=A0 0= x60: 0x0303e6ea 0xff00ff00 0xff00ff00 0x782000c0<br>=C2=A0 =C2=A0 0x70: 0x0= 0008088 0x00808888 0x00000000 0x00000000<br>=C2=A0 =C2=A0 0x80: 0xffcec458 = 0x40100040 0xffff0000 0x00000000<br>=C2=A0 =C2=A0 0x90: 0x00000002 0x000000= 00 0x00000000 0xffff0000<br>=C2=A0 =C2=A0 0xa0: 0x80ffffff 0x00000000 0x000= 00000 0x00000000<br>=C2=A0 =C2=A0 0xb0: 0x00000000 0x00000000 0x00000000 0x= 00000000<br>=C2=A0 =C2=A0 0xc0: 0x00000000 0x00000000 0x00000000 0x00000000= <br>=C2=A0 =C2=A0 0xd0: 0x00000000 0x00000000 0x00000000 0x00000000<br>=C2= =A0 =C2=A0 0xe0: 0x00000000 0x00000000 0x00000000 0x00000000<br>=C2=A0 =C2= =A0 0xf0: 0x00000000 0x00000000 0x00000000 0x00000000<br>PCI configuration = registers:<br>=C2=A0 Common header:<br>=C2=A0 =C2=A0 0x00: 0x00081039 0x020= 00007 0x06010001 0x00800000<br><br>=C2=A0 =C2=A0 Vendor Name: Silicon Integ= rated System (0x1039)<br>=C2=A0 =C2=A0 Device Name: 85C503 or 5597/5598 ISA= Bridge (0x0008)<br>=C2=A0 =C2=A0 Command register: 0x0007<br>=C2=A0 =C2=A0= =C2=A0 I/O space accesses: on<br>=C2=A0 =C2=A0 =C2=A0 Memory space accesse= s: on<br>=C2=A0 =C2=A0 =C2=A0 Bus mastering: on<br>=C2=A0 =C2=A0 =C2=A0 Spe= cial cycles: off<br>=C2=A0 =C2=A0 =C2=A0 MWI transactions: off<br>=C2=A0 = =C2=A0 =C2=A0 Palette snooping: off<br>=C2=A0 =C2=A0 =C2=A0 Parity error ch= ecking: off<br>=C2=A0 =C2=A0 =C2=A0 Address/data stepping: off<br>=C2=A0 = =C2=A0 =C2=A0 System error (SERR): off<br>=C2=A0 =C2=A0 =C2=A0 Fast back-to= -back transactions: off<br>=C2=A0 =C2=A0 =C2=A0 Interrupt disable: off<br>= =C2=A0 =C2=A0 Status register: 0x0200<br>=C2=A0 =C2=A0 =C2=A0 Immediate Rea= diness: off<br>=C2=A0 =C2=A0 =C2=A0 Interrupt status: inactive<br>=C2=A0 = =C2=A0 =C2=A0 Capability List support: off<br>=C2=A0 =C2=A0 =C2=A0 66 MHz c= apable: off<br>=C2=A0 =C2=A0 =C2=A0 User Definable Features (UDF) support: = off<br>=C2=A0 =C2=A0 =C2=A0 Fast back-to-back capable: off<br>=C2=A0 =C2=A0= =C2=A0 Data parity error detected: off<br>=C2=A0 =C2=A0 =C2=A0 DEVSEL timi= ng: medium (0x1)<br>=C2=A0 =C2=A0 =C2=A0 Slave signaled Target Abort: off<b= r>=C2=A0 =C2=A0 =C2=A0 Master received Target Abort: off<br>=C2=A0 =C2=A0 = =C2=A0 Master received Master Abort: off<br>=C2=A0 =C2=A0 =C2=A0 Asserted S= ystem Error (SERR): off<br>=C2=A0 =C2=A0 =C2=A0 Parity error detected: off<= br>=C2=A0 =C2=A0 Class Name: bridge (0x06)<br>=C2=A0 =C2=A0 Subclass Name: = ISA (0x01)<br>=C2=A0 =C2=A0 Interface: 0x00<br>=C2=A0 =C2=A0 Revision ID: 0= x01<br>=C2=A0 =C2=A0 BIST: 0x00<br>=C2=A0 =C2=A0 Header Type: 0x00+multifun= ction (0x80)<br>=C2=A0 =C2=A0 Latency Timer: 0x00<br>=C2=A0 =C2=A0 Cache Li= ne Size: 0bytes (0x00)<br><br>=C2=A0 Type 0 ("normal" device) hea= der:<br>=C2=A0 =C2=A0 0x10: 0x00000000 0x00000000 0x00000000 0x00000000<br>= =C2=A0 =C2=A0 0x20: 0x00000000 0x00000000 0x00000000 0x00000000<br>=C2=A0 = =C2=A0 0x30: 0x00000000 0x00000000 0x00000000 0x00000000<br><br>=C2=A0 =C2= =A0 Base address register at 0x10<br>=C2=A0 =C2=A0 =C2=A0 not implemented<b= r>=C2=A0 =C2=A0 Base address register at 0x14<br>=C2=A0 =C2=A0 =C2=A0 not i= mplemented<br>=C2=A0 =C2=A0 Base address register at 0x18<br>=C2=A0 =C2=A0 = =C2=A0 not implemented<br>=C2=A0 =C2=A0 Base address register at 0x1c<br>= =C2=A0 =C2=A0 =C2=A0 not implemented<br>=C2=A0 =C2=A0 Base address register= at 0x20<br>=C2=A0 =C2=A0 =C2=A0 not implemented<br>=C2=A0 =C2=A0 Base addr= ess register at 0x24<br>=C2=A0 =C2=A0 =C2=A0 not implemented<br>=C2=A0 =C2= =A0 Cardbus CIS Pointer: 0x00000000<br>=C2=A0 =C2=A0 Subsystem vendor ID: 0= x0000<br>=C2=A0 =C2=A0 Subsystem ID: 0x0000<br>=C2=A0 =C2=A0 Expansion ROM = Base Address Register: 0x00000000<br>=C2=A0 =C2=A0 =C2=A0 base: 0x00000000<= br>=C2=A0 =C2=A0 =C2=A0 Expansion ROM Enable: off<br>=C2=A0 =C2=A0 =C2=A0 V= alidation Status: Validation not supported<br>=C2=A0 =C2=A0 =C2=A0 Validati= on Details: 0x0<br>=C2=A0 =C2=A0 Reserved @ 0x34: 0x00000000<br>=C2=A0 =C2= =A0 Reserved @ 0x38: 0x00000000<br>=C2=A0 =C2=A0 Maximum Latency: 0x00<br>= =C2=A0 =C2=A0 Minimum Grant: 0x00<br>=C2=A0 =C2=A0 Interrupt pin: 0x00 (non= e)<br>=C2=A0 =C2=A0 Interrupt line: 0x00<br><br>=C2=A0 Device-dependent hea= der:<br>=C2=A0 =C2=A0 0x40: 0x0b800ffa 0x06006480 0x0f1000ff 0x01042011<br>= =C2=A0 =C2=A0 0x50: 0x01022811 0x0a670a62 0x00122e9c 0x000004a8<br>=C2=A0 = =C2=A0 0x60: 0x004f8032 0x80015b00 0x00120000 0x00001c20<br>=C2=A0 =C2=A0 0= x70: 0x0000001e 0xa325a321 0x00000000 0x00000000<br>=C2=A0 =C2=A0 0x80: 0x0= 0000000 0x00000000 0x00000000 0x00000000<br>=C2=A0 =C2=A0 0x90: 0x00003f00 = 0x00000000 0x00000000 0x00000000<br>=C2=A0 =C2=A0 0xa0: 0x00000000 0x000000= 00 0x00000000 0x00000000<br>=C2=A0 =C2=A0 0xb0: 0x00000000 0x00000000 0x000= 00000 0x00000000<br>=C2=A0 =C2=A0 0xc0: 0x00000000 0x00000000 0x00000000 0x= 00000000<br>=C2=A0 =C2=A0 0xd0: 0x00000000 0x00000000 0x00000000 0x00000000= <br>=C2=A0 =C2=A0 0xe0: 0x00000000 0x00000000 0x00000000 0x00000000<br>=C2= =A0 =C2=A0 0xf0: 0x00000000 0x00000000 0x00000000 0x00000000<br>PCI configu= ration registers:<br>=C2=A0 Common header:<br>=C2=A0 =C2=A0 0x00: 0x0900103= 9 0x02900107 0x02000002 0x0000d000<br><br>=C2=A0 =C2=A0 Vendor Name: Silico= n Integrated System (0x1039)<br>=C2=A0 =C2=A0 Device Name: 900 10/100 Ether= net (0x0900)<br>=C2=A0 =C2=A0 Command register: 0x0107<br>=C2=A0 =C2=A0 =C2= =A0 I/O space accesses: on<br>=C2=A0 =C2=A0 =C2=A0 Memory space accesses: o= n<br>=C2=A0 =C2=A0 =C2=A0 Bus mastering: on<br>=C2=A0 =C2=A0 =C2=A0 Special= cycles: off<br>=C2=A0 =C2=A0 =C2=A0 MWI transactions: off<br>=C2=A0 =C2=A0= =C2=A0 Palette snooping: off<br>=C2=A0 =C2=A0 =C2=A0 Parity error checking= : off<br>=C2=A0 =C2=A0 =C2=A0 Address/data stepping: off<br>=C2=A0 =C2=A0 = =C2=A0 System error (SERR): on<br>=C2=A0 =C2=A0 =C2=A0 Fast back-to-back tr= ansactions: off<br>=C2=A0 =C2=A0 =C2=A0 Interrupt disable: off<br>=C2=A0 = =C2=A0 Status register: 0x0290<br>=C2=A0 =C2=A0 =C2=A0 Immediate Readiness:= off<br>=C2=A0 =C2=A0 =C2=A0 Interrupt status: inactive<br>=C2=A0 =C2=A0 = =C2=A0 Capability List support: on<br>=C2=A0 =C2=A0 =C2=A0 66 MHz capable: = off<br>=C2=A0 =C2=A0 =C2=A0 User Definable Features (UDF) support: off<br>= =C2=A0 =C2=A0 =C2=A0 Fast back-to-back capable: on<br>=C2=A0 =C2=A0 =C2=A0 = Data parity error detected: off<br>=C2=A0 =C2=A0 =C2=A0 DEVSEL timing: medi= um (0x1)<br>=C2=A0 =C2=A0 =C2=A0 Slave signaled Target Abort: off<br>=C2=A0= =C2=A0 =C2=A0 Master received Target Abort: off<br>=C2=A0 =C2=A0 =C2=A0 Ma= ster received Master Abort: off<br>=C2=A0 =C2=A0 =C2=A0 Asserted System Err= or (SERR): off<br>=C2=A0 =C2=A0 =C2=A0 Parity error detected: off<br>=C2=A0= =C2=A0 Class Name: network (0x02)<br>=C2=A0 =C2=A0 Subclass Name: ethernet= (0x00)<br>=C2=A0 =C2=A0 Interface: 0x00<br>=C2=A0 =C2=A0 Revision ID: 0x02= <br>=C2=A0 =C2=A0 BIST: 0x00<br>=C2=A0 =C2=A0 Header Type: 0x00 (0x00)<br>= =C2=A0 =C2=A0 Latency Timer: 0xd0<br>=C2=A0 =C2=A0 Cache Line Size: 0bytes = (0x00)<br><br>=C2=A0 Type 0 ("normal" device) header:<br>=C2=A0 = =C2=A0 0x10: 0x00004001 0x60000000 0x00000000 0x00000000<br>=C2=A0 =C2=A0 0= x20: 0x00000000 0x00000000 0x00000000 0x09001039<br>=C2=A0 =C2=A0 0x30: 0x0= 0000000 0x00000040 0x00000000 0x0b34010f<br><br>=C2=A0 =C2=A0 Base address = register at 0x10<br>=C2=A0 =C2=A0 =C2=A0 type: I/O<br>=C2=A0 =C2=A0 =C2=A0 = base: 0x00004000<br>=C2=A0 =C2=A0 Base address register at 0x14<br>=C2=A0 = =C2=A0 =C2=A0 type: 32-bit nonprefetchable memory<br>=C2=A0 =C2=A0 =C2=A0 b= ase: 0x60000000<br>=C2=A0 =C2=A0 Base address register at 0x18<br>=C2=A0 = =C2=A0 =C2=A0 not implemented<br>=C2=A0 =C2=A0 Base address register at 0x1= c<br>=C2=A0 =C2=A0 =C2=A0 not implemented<br>=C2=A0 =C2=A0 Base address reg= ister at 0x20<br>=C2=A0 =C2=A0 =C2=A0 not implemented<br>=C2=A0 =C2=A0 Base= address register at 0x24<br>=C2=A0 =C2=A0 =C2=A0 not implemented<br>=C2=A0= =C2=A0 Cardbus CIS Pointer: 0x00000000<br>=C2=A0 =C2=A0 Subsystem vendor I= D: 0x1039<br>=C2=A0 =C2=A0 Subsystem ID: 0x0900<br>=C2=A0 =C2=A0 Expansion = ROM Base Address Register: 0x00000000<br>=C2=A0 =C2=A0 =C2=A0 base: 0x00000= 000<br>=C2=A0 =C2=A0 =C2=A0 Expansion ROM Enable: off<br>=C2=A0 =C2=A0 =C2= =A0 Validation Status: Validation not supported<br>=C2=A0 =C2=A0 =C2=A0 Val= idation Details: 0x0<br>=C2=A0 =C2=A0 Capability list pointer: 0x40<br>=C2= =A0 =C2=A0 Reserved @ 0x38: 0x00000000<br>=C2=A0 =C2=A0 Maximum Latency: 0x= 0b<br>=C2=A0 =C2=A0 Minimum Grant: 0x34<br>=C2=A0 =C2=A0 Interrupt pin: 0x0= 1 (pin A)<br>=C2=A0 =C2=A0 Interrupt line: 0x0f<br><br>=C2=A0 Capability re= gister at 0x40<br>=C2=A0 =C2=A0 type: 0x01 (Power Management)<br><br>=C2=A0= PCI Power Management Capabilities Register<br>=C2=A0 =C2=A0 Capabilities r= egister: 0xfe01<br>=C2=A0 =C2=A0 =C2=A0 Version: 1.0<br>=C2=A0 =C2=A0 =C2= =A0 PME# clock: off<br>=C2=A0 =C2=A0 =C2=A0 Device specific initialization:= off<br>=C2=A0 =C2=A0 =C2=A0 3.3V auxiliary current: self-powered<br>=C2=A0= =C2=A0 =C2=A0 D1 power management state support: on<br>=C2=A0 =C2=A0 =C2= =A0 D2 power management state support: on<br>=C2=A0 =C2=A0 =C2=A0 PME# supp= ort D0: on<br>=C2=A0 =C2=A0 =C2=A0 PME# support D1: on<br>=C2=A0 =C2=A0 =C2= =A0 PME# support D2: on<br>=C2=A0 =C2=A0 =C2=A0 PME# support D3 hot: on<br>= =C2=A0 =C2=A0 =C2=A0 PME# support D3 cold: on<br>=C2=A0 =C2=A0 Control/stat= us register: 0x00000000<br>=C2=A0 =C2=A0 =C2=A0 Power state: D0<br>=C2=A0 = =C2=A0 =C2=A0 PCI Express reserved: off<br>=C2=A0 =C2=A0 =C2=A0 No soft res= et: off<br>=C2=A0 =C2=A0 =C2=A0 PME# assertion: disabled<br>=C2=A0 =C2=A0 = =C2=A0 Data Select: 0<br>=C2=A0 =C2=A0 =C2=A0 Data Scale: 0<br>=C2=A0 =C2= =A0 =C2=A0 PME# status: off<br>=C2=A0 =C2=A0 Bridge Support Extensions regi= ster: 0x00<br>=C2=A0 =C2=A0 =C2=A0 B2/B3 support: off<br>=C2=A0 =C2=A0 =C2= =A0 Bus Power/Clock Control Enable: off<br>=C2=A0 =C2=A0 Data register: 0x0= 0<br><br>=C2=A0 Device-dependent header:<br>=C2=A0 =C2=A0 0x40: 0xfe010001 = 0x00000000 0x00000000 0x00000000<br>=C2=A0 =C2=A0 0x50: 0x00000000 0x000000= 00 0x00000000 0x00000000<br>=C2=A0 =C2=A0 0x60: 0x00000000 0x00000000 0x000= 00000 0x00000000<br>=C2=A0 =C2=A0 0x70: 0x00000000 0x00000000 0x00000000 0x= 00000000<br>=C2=A0 =C2=A0 0x80: 0x00000000 0x00000000 0x00000000 0x00000000= <br>=C2=A0 =C2=A0 0x90: 0x00000000 0x00000000 0x00000000 0x00000000<br>=C2= =A0 =C2=A0 0xa0: 0x00000000 0x00000000 0x00000000 0x00000000<br>=C2=A0 =C2= =A0 0xb0: 0x00000000 0x00000000 0x00000000 0x00000000<br>=C2=A0 =C2=A0 0xc0= : 0x00000000 0x00000000 0x00000000 0x00000000<br>=C2=A0 =C2=A0 0xd0: 0x0000= 0000 0x00000000 0x00000000 0x00000000<br>=C2=A0 =C2=A0 0xe0: 0x00000000 0x0= 0000000 0x00000000 0x00000000<br>=C2=A0 =C2=A0 0xf0: 0x00000000 0x00000000 = 0x00000000 0x00000000<br>pcictl: "08" is not a number</div></div>= </div></blockquote><div><br></div><div>And here is the IDE controller:<br><= br> 586ve$ pcictl pci0 dump -b 000 -d 01 -f 1<br>PCI configuration register= s:<br>=C2=A0 Common header:<br>=C2=A0 =C2=A0 0x00: 0x55131039 0x00000001 0x= 01018ad0 0x00800000<br><br>=C2=A0 =C2=A0 Vendor Name: Silicon Integrated Sy= stem (0x1039)<br>=C2=A0 =C2=A0 Device Name: 5597/5598 IDE Controller (0x551= 3)<br>=C2=A0 =C2=A0 Command register: 0x0001<br>=C2=A0 =C2=A0 =C2=A0 I/O sp= ace accesses: on<br>=C2=A0 =C2=A0 =C2=A0 Memory space accesses: off<br>=C2= =A0 =C2=A0 =C2=A0 Bus mastering: off<br>=C2=A0 =C2=A0 =C2=A0 Special cycles= : off<br>=C2=A0 =C2=A0 =C2=A0 MWI transactions: off<br>=C2=A0 =C2=A0 =C2=A0= Palette snooping: off<br>=C2=A0 =C2=A0 =C2=A0 Parity error checking: off<b= r>=C2=A0 =C2=A0 =C2=A0 Address/data stepping: off<br>=C2=A0 =C2=A0 =C2=A0 S= ystem error (SERR): off<br>=C2=A0 =C2=A0 =C2=A0 Fast back-to-back transacti= ons: off<br>=C2=A0 =C2=A0 =C2=A0 Interrupt disable: off<br>=C2=A0 =C2=A0 St= atus register: 0x0000<br>=C2=A0 =C2=A0 =C2=A0 Immediate Readiness: off<br>= =C2=A0 =C2=A0 =C2=A0 Interrupt status: inactive<br>=C2=A0 =C2=A0 =C2=A0 Cap= ability List support: off<br>=C2=A0 =C2=A0 =C2=A0 66 MHz capable: off<br>= =C2=A0 =C2=A0 =C2=A0 User Definable Features (UDF) support: off<br>=C2=A0 = =C2=A0 =C2=A0 Fast back-to-back capable: off<br>=C2=A0 =C2=A0 =C2=A0 Data p= arity error detected: off<br>=C2=A0 =C2=A0 =C2=A0 DEVSEL timing: fast (0x0)= <br>=C2=A0 =C2=A0 =C2=A0 Slave signaled Target Abort: off<br>=C2=A0 =C2=A0 = =C2=A0 Master received Target Abort: off<br>=C2=A0 =C2=A0 =C2=A0 Master rec= eived Master Abort: off<br>=C2=A0 =C2=A0 =C2=A0 Asserted System Error (SERR= ): off<br>=C2=A0 =C2=A0 =C2=A0 Parity error detected: off<br>=C2=A0 =C2=A0 = Class Name: mass storage (0x01)<br>=C2=A0 =C2=A0 Subclass Name: IDE (0x01)<= br>=C2=A0 =C2=A0 Interface: 0x8a<br>=C2=A0 =C2=A0 Revision ID: 0xd0<br>=C2= =A0 =C2=A0 BIST: 0x00<br>=C2=A0 =C2=A0 Header Type: 0x00+multifunction (0x8= 0)<br>=C2=A0 =C2=A0 Latency Timer: 0x00<br>=C2=A0 =C2=A0 Cache Line Size: 0= bytes (0x00)<br><br>=C2=A0 Type 0 ("normal" device) header:<br>= =C2=A0 =C2=A0 0x10: 0x00002001 0x00002101 0x00002201 0x00002301<br>=C2=A0 = =C2=A0 0x20: 0xfd64ffa1 0x00000000 0x00000000 0x1d97af69<br>=C2=A0 =C2=A0 0= x30: 0x00000000 0x00000000 0x00000000 0x00000100<br><br>=C2=A0 =C2=A0 Base = address register at 0x10<br>=C2=A0 =C2=A0 =C2=A0 type: I/O<br>=C2=A0 =C2=A0= =C2=A0 base: 0x00002000<br>=C2=A0 =C2=A0 Base address register at 0x14<br>= =C2=A0 =C2=A0 =C2=A0 type: I/O<br>=C2=A0 =C2=A0 =C2=A0 base: 0x00002100<br>= =C2=A0 =C2=A0 Base address register at 0x18<br>=C2=A0 =C2=A0 =C2=A0 type: I= /O<br>=C2=A0 =C2=A0 =C2=A0 base: 0x00002200<br>=C2=A0 =C2=A0 Base address r= egister at 0x1c<br>=C2=A0 =C2=A0 =C2=A0 type: I/O<br>=C2=A0 =C2=A0 =C2=A0 b= ase: 0x00002300<br>=C2=A0 =C2=A0 Base address register at 0x20<br>=C2=A0 = =C2=A0 =C2=A0 type: I/O<br>=C2=A0 =C2=A0 =C2=A0 base: 0xfd64ffa0<br>=C2=A0 = =C2=A0 Base address register at 0x24<br>=C2=A0 =C2=A0 =C2=A0 not implemente= d<br>=C2=A0 =C2=A0 Cardbus CIS Pointer: 0x00000000<br>=C2=A0 =C2=A0 Subsyst= em vendor ID: 0xaf69<br>=C2=A0 =C2=A0 Subsystem ID: 0x1d97<br>=C2=A0 =C2=A0= Expansion ROM Base Address Register: 0x00000000<br>=C2=A0 =C2=A0 =C2=A0 ba= se: 0x00000000<br>=C2=A0 =C2=A0 =C2=A0 Expansion ROM Enable: off<br>=C2=A0 = =C2=A0 =C2=A0 Validation Status: Validation not supported<br>=C2=A0 =C2=A0 = =C2=A0 Validation Details: 0x0<br>=C2=A0 =C2=A0 Reserved @ 0x34: 0x00000000= <br>=C2=A0 =C2=A0 Reserved @ 0x38: 0x00000000<br>=C2=A0 =C2=A0 Maximum Late= ncy: 0x00<br>=C2=A0 =C2=A0 Minimum Grant: 0x00<br>=C2=A0 =C2=A0 Interrupt p= in: 0x01 (pin A)<br>=C2=A0 =C2=A0 Interrupt line: 0x00<br><br>=C2=A0 Device= -dependent header:<br>=C2=A0 =C2=A0 0x40: 0x00000301 0x00000000 0x03220700 = 0x02000200<br>=C2=A0 =C2=A0 0x50: 0x000d0200 0x00000000 0x00000000 0x000000= 00<br>=C2=A0 =C2=A0 0x60: 0x00000000 0x00000000 0x00000000 0x00000000<br>= =C2=A0 =C2=A0 0x70: 0x00000000 0x00000000 0x00000000 0x00000000<br>=C2=A0 = =C2=A0 0x80: 0x00000000 0x00000000 0x00000000 0x00000000<br>=C2=A0 =C2=A0 0= x90: 0x00000000 0x00000000 0x00000000 0x00000000<br>=C2=A0 =C2=A0 0xa0: 0x0= 0000000 0x00000000 0x00000000 0x00000000<br>=C2=A0 =C2=A0 0xb0: 0x00000000 = 0x00000000 0x00000000 0x00000000<br>=C2=A0 =C2=A0 0xc0: 0x00000000 0x000000= 00 0x00000000 0x00000000<br>=C2=A0 =C2=A0 0xd0: 0x00000000 0x00000000 0x000= 00000 0x00000000<br>=C2=A0 =C2=A0 0xe0: 0x00000000 0x00000000 0x00000000 0x= 00000000<br>=C2=A0 =C2=A0 0xf0: 0x00000000 0x00000000 0x00000000 0x00000000= </div><div><br></div><div>- Alex<br></div></div></div></blockquote><div><br= ></div><div><div>Did this reveal any clues to the source of the problem?</d= iv><div><br></div><div>Thanks!</div><div>- Alex</div>=C2=A0</div></div></di= v> --000000000000514ff0061b2c90ef--