m68k cacheops header -- some questions

Hey folks,

Some questions about the m68k cacheops header:

1. The TBIS (TLB-invalidate-single) always operate on the user and =
supervisor side.  Is it worth having separate USER vs KERN versions of =
these operations to support systems that can do it (which I think =
includes the =E2=80=98851, =E2=80=98030, =E2=80=98040, and =E2=80=98060)? =
 Obviously the HP MMU doesn=E2=80=99t get to have this optimization.  =
Wildcard: I=E2=80=99m not certain what happens with the D-cache on the =
=E2=80=98030 (are the cache lines tagged with the function code?  I need =
to re-read the manual I guess=E2=80=A6)

2. What=E2=80=99s the difference between ICIA and ICPA?  As far as I can =
tell, they=E2=80=99re equivalent within each CPU+MMU tuple.

3. What=E2=80=99s with PCIA_20?  It uses the CACR, but the 68020 =
doesn=E2=80=99t have an on-chip D-cache, right?

4. Ditto with PCIA_30?  The name implies =E2=80=9Cphysical=E2=80=9D, =
which of course the 68030 D-cache is not.  I suppose this is there as a =
fall through for 68030 systems with external phys caches (if we=E2=80=99re=
 invalidating the external cache, we should invalidate the internal one, =
too).  Just confirming.

5. If so, why don=E2=80=99t we just have a single DCIA_30?

6. Why on earth doesn=E2=80=99t the m68k bus_dma invalidate the D-cache =
in the PREREAD (or POSTREAD, since the cache is write-through) case?

-- thorpej