arch/mac68k/obio/esp.c and resetting DRQ

Hi all,

I've been looking at arch/mac68k/obio/esp.c to try and understand how the SCSI DRQ 
signal gets reset on a Q800 and wonder if anyone has any real hardware or relevant 
experience. The background to this is that I'm working on a set of patches for QEMU 
that will enable the Q800 machine to boot MacOS, NetBSD and A/UX.

According to the GTTMFH the SCSI DRQ signal is connected to the CA2 control line in 
VIA2 (bit 0 in the IFR) and therefore this bit should be latched until either port A 
is read from/written to (input mode) or bit 0 is reset in the IFR (independent mode) 
by writing a 1.

However esp_iosb_have_dreq() simply checks bit 0 of the IFR "live" to look for DRQ 
and I don't see any writes to back to the IFR or accesses from VIA2 port A to reset 
the flag in IFR once again. This would suggest that using this code DRQ would always 
remain set after any SCSI IO.

Does anyone have any more detail as to how this mechanism works on real hardware? I'd 
be interested to know if esp_iosb_have_dreq() ever returns a value for the DRQ bit 
that isn't 1.


Many thanks,

Mark.