TLB-miss counter in TLB-miss handler (important proposal).
"Naruaki.Etomi" <[email protected]>
| Newsgroups | gmane.os.netbsd.ports.mips.devel |
|---|---|
| Message-ID | <CANkyS8XbCpNCvCQaAq6ypOwhMqyg_PPg0bAEbdCiWPnOE9qQ3w@mail.gmail.com> |
This is important proposal. ------------------------------------------------------------------------------------------- Prerequisite: %hi %lo operator that takes an address as an argument does not work on mips64 kernel. Like below: lui k1, %hi(CPUVAR(CURLWP)) #05: k1=hi of curlwp jr k0 #06 PTR_L k1, %lo(CPUVAR(CURLWP))(k1) #07: k1=lo of curlwp Because: LUI instruction means: The immediate value is shifted left "16 bits" and stored in the register. The lower 16 bits are zeroes. Adress 0x0011aabbccddeeff (64 bit) is processed as follows: lui k1, 0x0011aabbccddeeff -> k1 = 0xffffffffccde0000 PTR_L k1, %lo(0x0011aabbccddeeff)(k1) -> ld k1, 0xffffffffeeff0000(0xffffffffccde0000) -> Load from chaos! However, The higher 32bits are f adress(0xffffffffaabbccd like O2 etc) is work. makeoptions TEXTADDR="0xffffffff80069000" # entry point https://nxr.netbsd.org/xref/src/sys/arch/sgimips/conf/GENERIC64_IP3x#29 ------------------------------------------------------------------------------------------- I rewrite %hi %lo operator code. https://github.com/nullnilaki/NetBSD-mips64/commit/2729f32536de2fedefdd5d828f6fa918d991e555 And I discovered below. https://nxr.netbsd.org/xref/src/sys/arch/mips/mips/mipsX_subr.S#498 #if (MIPS3 + MIPS64 + MIPS64R2) > 0 lui k1, %hi(CPUVAR(EV_TLBMISSES)) #1b: k1=hi of tlbmisses REG_L k0, %lo(CPUVAR(EV_TLBMISSES))(k1) #1c REG_ADDU k0, 1 #1d REG_S k0, %lo(CPUVAR(EV_TLBMISSES))(k1) #1e #endif I rewrite this code. Like below: +#if (MIPS3 + MIPS64 + MIPS64R2) > 0 + dla k1, (CPUVAR(EV_TLBMISSES)) + ld k0, 0(k1) #1c + REG_ADDU k0, 1 #1d + sd k0, 0(k1) #1e +#endif Howerver, There are many instructions... --- mips3_subr.o --- /usr/src/sys/arch/mips/mips/mipsX_subr.S: Assembler messages: /usr/src/sys/arch/mips/mips/mipsX_subr.S:509: Error: attempt to move .org backwards /usr/src/sys/arch/mips/mips/mipsX_subr.S:660: Error: attempt to move .org backwards *** [mips3_subr.o] Error code 1 ------------------------------------------------------------------------------------------- I think TLB-miss handler should be especially simple. I want to delete TLB-miss counter code. Like below: https://github.com/nullnilaki/NetBSD-mips64/commit/c13ff030cffbd90f69e2fe438204a7f630f2ffb9 Please confirm that I may take this course of action. -- Naruaki Etomi [email protected]