Re: SGI MIPS, Speculative Execution issue

> The first thing I don't understand is what does it mean that they are
> "Non-Cache Coherent" systems.

Maybe the following text would help:
 "Unix Systems for Modern Architectures: Symmetric Multiprocessing and Caching for Kernel Programmers"
 https://www.amazon.com/dp/0201633388

and also NetBSD's bus_dma(9) paper:
 "A Machine-Independent DMA Framework for NetBSD"
 https://www.netbsd.org/docs/kernel/bus_dma.pdf

>> The semantics of the host systemfs cache are also
>> important to devices which wish to perform DMA.
>> Some systems are capable of cache-coherent DMA. On
>> such systems, the cache is often write-through (i.e.
>> stores are written both to the cache and to host mem-
>> ory), or the cache has special snooping logic that can
>> detect access to a memory location for which there is a
>> dirty cache line (which causes the cache to be flushed
>> automatically). Other systems are not capable of cache-
>> coherent DMA. On these systems, software must
>> explicitly flush any data caches before memory-to-
>> device DMA transfers, as well as invalidate soon-to-be-
>> stale cache lines before device-to-memory DMA.

Actually O2 doesn't have bus-snoop, as far as I could see when
I implemented NetBSD's mec(4) and other NIC drivers.
(and it looked SGI used "cacheline size" DMA descriptors to handle it)
 
---
Izumi Tsutsui