Re: SGI MIPS, Speculative Execution issue

 [[ non-cache-coherent question, rather than speculative execution ]]

For uniprocessor MIPS systems, "non-cache-coherent" usually means that changing memory via DMA is not reflected in the caches.
Software has to explicitly invalidate any cache entries for a page, after a DMA write (I/O read operation) on a page completes. That includes both I-cache(s) and D-cache(s). If your caches are write-back rather than write-through, you may also need to push any matching (and therefore dirty) D-cache lines to memory, before a DMA read (I/O write operation).

The I-cache and D-cache are also not coherent with each other. So if you modify code on the fly -- for example, setting a breakpoint by writing an invalid instruction into code -- you will need to flush any possible I-cache hit for the modified memory location(s).

The above is accurate for MIPS R2000A/R3000 and R4000/R4400. I've not personally delved that deep on an R10000.