Re: New MIPS cache code vs. R5k secondary caches...

On Fri, Sep 20, 2002 at 07:21:24PM -0400, Rafal Boni wrote:

 > In message <[email protected]>, you write: 
 > 
 > -> On Fri, Sep 20, 2002 at 04:24:00PM -0400, Rafal Boni wrote:
 > -> 
 > ->  > 		* First of all, Jason noted that he'd verified RM5260 worked
 > ->  > 		  on his P5064; was this with L2 or without?
 > -> 
 > -> As far as I know, none of the QED (now PMC-Sierra) RM52xx CPUs have an
 > -> L2 cache interface.  Obviously, mine was tested without :-)
 > 
 > Ah!  I did register for doc access at PMC-Sierra after I sent the previous
 > mail, and grabbed the manual and errata, but haven't read any of it yet.

My mistake -- the RM527x have an L2 cache interface.

Possible sizes are 512K, 1M, 2M.  L2 cache is physically indexed and
physically tagged.  32 bytes/line.

Regarding the Page_Invalidate cache op, the RM52xx manual says:

	The processor performs a burst of 128 Index_Store_Tag
	operations to the secondary cache at the page specified
	by the effective address generated by the CACHE instruction,
	which must be page-aligned.  To invalidate the page, the
	state bits within the TagLo register must be zero.  Interrupts
	are deferred during this operation.

-- 
        -- Jason R. Thorpe <[email protected]>