Re: Servicing Multiple (nested) TLB Misses

"Jason R Thorpe" <[email protected]> commented;

>  >                         /* detour lw fault during UTLBmiss; MIPS1 only */
>  >                         if (cpu_arch == CPU_ARCH_MIPS1
>  >                              && opc == (0x80000000+sizeof(int)*2))
>  >                                 frame->f_pc = 0x80000000+sizeof(int)*7;
> 
> So, I see that you write the TLB entry for the PT page... but then you
> skip the "tlbwr" for the original UTLBMiss fault ... so, I guess it
> restarts the instruction, faults again, and now the PT page will be
> in the TLB ... okay, that makes sense, but the double fault is kind of
> unfortunate.  It would be nice to instrument how often the double-fault
> case happens.

Ah, the portion is an excess and can be eliminated.

>  > In short, it's done just like as what NetBSD/i386 or NetBSD/pc532
>  > "fools" their MMU.
> 
> This is precicely how the Alpha works, as well (except the Alpha uses a
> 3-level table, rather than 2-level).  The Alpha hardware is actually a
> software-managed TLB, like MIPS, but the TLB miss handlers are all in
> PALcode.

The same techniq can be useful for other software managed TLB processors.
SH3 and MPC850/860 fall in that category.  And I'm watching with a great
interest at Steve Woodford's SH5 pmap wondering it can be a basis of
64bit PTR (say, pmap64.c) NetBSD/mips.

Toru Nishimura/ALKYL Technology