Re: 64-bit Malta Kernel/Userland/Toolchain?

On Wed, Jul 03, 2002 at 08:20:41PM -0700, [email protected] wrote:

 > At Thu, 4 Jul 2002 02:43:17 +0000 (UTC), "Toru Nishimura" wrote:
 > > alpha PTE manipulation is done in table-walk for user address space even though
 > > kernel PTE is handsomely thru VPT.
 > 
 > Wow, really?
 > 
 > That's surprising to me.  Do you have a cite?  (I'd be interested in
 > reading the research that motivated the implementation, if it's
 > available!)

I think Nisimura-san is referring to the pmap module, whch does use
a table talk for user-space addresses to manipulate PTEs .. it does
so because user PT pages are allocated on-demand.

The pmap module does use the VPT for kernel PTEs.

And the TLB refill handler in the PALcode always uses the VPT.

The PALcode uses the ldq_p (Load Quadword Physical) insn to load the
PTE through the linear VPT mapping... sort of.  It actually uses the
,v ("but, actually, do it with a virtual address") modifier.  Which
means that it has exactly the same behavior as a normal ldq, but it
has a different opcode (an opcode which is reserved for PAL mode).

So, in the TLB miss handler, the PALcode first checks to see if the
faulting insn was an ldq_p,v, and if so, does a table-walk (using a
normal ldq_p) to load a TLB entry for the VPT address that's being
accessed, then returns from the fault, and the ldq_p,v succeeds, and
a TLB entry is loaded for the original miss address.

-- 
        -- Jason R. Thorpe <[email protected]>