Re: compat/native?

Tim Rightnour wrote:

>> And the IDE interrupt routine register (0x4c) is fixed to 15/14 on the
>> 8231, you cannot change it to 14/14, according to the specs. Maybe this
>> is the "feature" causing the observed behaviour?
> 
> Given that it works if you do this, and you are having problems getting it
> to do something else, I'm more inclined to figure out how to make it use
> both irqs than I am to fiddle around with the modes.

The real problem is to do it in a clean way. The pciide_common.c code cannot
deal with more than one irq in native mode. It calls pci_intr_map() for each
channel, but twice with a pointer to the pci_attach_args of the same IDE
controller device. Both return 14.

The question is, is that a bug of the VT8231, which is exploited here, or is
it a feature, which should officially be supported by pciide_common.c or
viaide.c?

When we cannot officially support it, the hack will look ugly. ;)


> Just so everyone is on the same page, here is the pci regs for my pcib on
> my pegasos-II:
> 
> Device-dependent header:
>    0x40: 0x00007f04 0x0003764e 0x00000000 0x00000304
>    0x50: 0x00003d03 0x90999000 0x00000000 0x00000000
>    0x60: 0x00000000 0x08000000 0x00000001 0x00000000
>    0x70: 0x00000000 0x00000000 0x00000000 0x00000020
>    0x80: 0x00000000 0x00000000 0x00000000 0x00000000
>    0x90: 0x00000000 0x00000000 0x00000000 0x00000000
>    0xa0: 0x00000000 0x00000000 0x00000000 0x00000000
>    0xb0: 0x00000000 0x00000000 0x00000000 0x00000000
>    0xc0: 0x00020001 0x00000000 0x00000000 0x00000000
>    0xd0: 0x00000000 0x00000000 0x00000000 0x00000000
>    0xe0: 0x00000000 0x00000000 0x00000000 0x00000000
>    0xf0: 0x00000000 0x00150000 0x00000000 0x00000000

Exactly the same here.

You see the 0x04 at offset 0x4c (your dump has to be byte-reversed), which
means IRQ 15 for secondary channel.


-- 
    _  Frank Wille ([email protected])
 _ //  http://sun.hasenbraten.de/~frank/
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