powerpc/booke MULTIPROCESSOR

Index: sys/arch/powerpc/booke/booke_pmap.c
===================================================================
RCS file: /cvsroot/src/sys/arch/powerpc/booke/booke_pmap.c,v
retrieving revision 1.21
diff -u -r1.21 booke_pmap.c
--- sys/arch/powerpc/booke/booke_pmap.c	23 Jan 2015 06:39:41 -0000	1.21
+++ sys/arch/powerpc/booke/booke_pmap.c	23 Jan 2015 09:08:03 -0000
@@ -43,11 +43,16 @@
 #include <sys/param.h>
 #include <sys/kcore.h>
 #include <sys/buf.h>
+#include <sys/mutex.h>
 
 #include <uvm/uvm.h>
 
 #include <machine/pmap.h>
 
+#if defined(MULTIPROCESSOR)
+kmutex_t pmap_tlb_miss_lock;
+#endif
+
 /*
  * Initialize the kernel pmap.
  */
@@ -166,6 +171,10 @@
 	/* init the lock */
 	pmap_tlb_info_init(&pmap_tlb0_info);
 
+#if defined(MULTIPROCESSOR)
+	mutex_init(&pmap_tlb_miss_lock, MUTEX_SPIN, IPL_HIGH);
+#endif
+
 	/*
 	 * Compute the number of pages kmem_arena will have.
 	 */
@@ -427,4 +436,18 @@
 {
 	/* nothing */
 }
+
+void
+pmap_md_tlb_miss_lock_enter(void)
+{
+
+	mutex_spin_enter(&pmap_tlb_miss_lock);
+}
+
+void
+pmap_md_tlb_miss_lock_exit(void)
+{
+
+	mutex_spin_exit(&pmap_tlb_miss_lock);
+}
 #endif /* MULTIPROCESSOR */
Index: sys/arch/powerpc/booke/genassym.cf
===================================================================
RCS file: /cvsroot/src/sys/arch/powerpc/booke/genassym.cf,v
retrieving revision 1.10
diff -u -r1.10 genassym.cf
--- sys/arch/powerpc/booke/genassym.cf	27 Nov 2012 19:24:46 -0000	1.10
+++ sys/arch/powerpc/booke/genassym.cf	23 Jan 2015 09:08:03 -0000
@@ -111,4 +111,7 @@
 define	HATCH_TBU		offsetof(struct cpu_hatch_data, hatch_tbu)
 define	HATCH_TBL		offsetof(struct cpu_hatch_data, hatch_tbl)
 define	HATCH_TLBIDX		offsetof(struct cpu_hatch_data, hatch_tlbidx)
+
+define	__SIMPLELOCK_LOCKED	__SIMPLELOCK_LOCKED
+define	__SIMPLELOCK_UNLOCKED	__SIMPLELOCK_UNLOCKED
 endif
Index: sys/arch/powerpc/booke/trap_subr.S
===================================================================
RCS file: /cvsroot/src/sys/arch/powerpc/booke/trap_subr.S,v
retrieving revision 1.11
diff -u -r1.11 trap_subr.S
--- sys/arch/powerpc/booke/trap_subr.S	18 Sep 2014 23:37:51 -0000	1.11
+++ sys/arch/powerpc/booke/trap_subr.S	23 Jan 2015 09:08:03 -0000
@@ -346,6 +346,50 @@
 	RESTORE_SPRG1(%r6);	\
 	FRAME_INTR_XEXIT(rfci, CSRR)
 
+#if defined(MULTIPROCESSOR)
+#define	FRAME_TLBMISSLOCK						\
+	GET_CPUINFO(%r23);						\
+	ldint	%r22, CI_MTX_COUNT(%r23);				\
+	subi	%r22, %r22, 1;						\
+	stint	%r22, CI_MTX_COUNT(%r23);				\
+	isync;								\
+	cmpwi	%r22, 0;						\
+	bne	1f;							\
+	ldint	%r22, CI_CPL(%r23);					\
+	stint	%r22, CI_MTX_OLDSPL(%r23);				\
+1:	lis	%r23, _C_LABEL(pmap_tlb_miss_lock)@h;			\
+	ori	%r23, %r23, _C_LABEL(pmap_tlb_miss_lock)@l;		\
+	li	%r20, MTX_LOCK;						\
+2:	lwarx	%r22, %r20, %r23;					\
+	cmpwi	%r22, __SIMPLELOCK_UNLOCKED;				\
+	beq+	4f;							\
+3:	lwzx	%r22, %r20, %r23;					\
+	cmpwi	%r22, __SIMPLELOCK_UNLOCKED;				\
+	beq+	2b;							\
+	b	3b;							\
+4:	li	%r21, __SIMPLELOCK_LOCKED;				\
+	stwcx.	%r21, %r20, %r23;					\
+	bne-	2b;							\
+	isync;								\
+	msync;
+#define	FRAME_TLBMISSUNLOCK						\
+	sync;								\
+	lis	%r23, _C_LABEL(pmap_tlb_miss_lock)@h;			\
+	ori	%r23, %r23, _C_LABEL(pmap_tlb_miss_lock)@l;		\
+	li	%r22, __SIMPLELOCK_UNLOCKED;				\
+	stw	%r22, MTX_LOCK(%r23);					\
+	isync;								\
+	msync;								\
+	GET_CPUINFO(%r23);						\
+	ldint	%r22, CI_MTX_COUNT(%r23);				\
+	addi	%r22, %r22, 1;						\
+	stint	%r22, CI_MTX_COUNT(%r23);				\
+	isync;
+#else	/* !MULTIPROCESSOR */
+#define	FRAME_TLBMISSLOCK
+#define	FRAME_TLBMISSUNLOCK
+#endif	/* MULTIPROCESSOR */
+
 	.text
 	.p2align 4
 _C_LABEL(critical_input_vector):
@@ -535,6 +579,7 @@
 _C_LABEL(data_tlb_error_vector):
 	/* MSR[CE], MSR[ME], MSR[DE] are unchanged, all others cleared */
 	FRAME_TLBPROLOGUE
+	FRAME_TLBMISSLOCK
 	/*
 	 * Registers as this point:
 	 *
@@ -577,6 +622,7 @@
 		31-PTR_SCALESHIFT, \
 		31-PTR_SCALESHIFT		/* move PSL_DS[27] to bit 29 */
 	bl	pte_load
+	FRAME_TLBMISSUNLOCK
 	mtlr	%r29				/* restore LR */
 	/*
 	 * If we returned, pte load failed so let trap deal with it but
@@ -590,6 +636,7 @@
 _C_LABEL(instruction_tlb_error_vector):
 	/* MSR[CE], MSR[ME], MSR[DE] are unchanged, all others cleared */
 	FRAME_TLBPROLOGUE
+	FRAME_TLBMISSLOCK
 	/*
 	 * Attempt to update the TLB from the page table.
 	 */
@@ -600,6 +647,7 @@
 		31-PTR_SCALESHIFT, \
 		31-PTR_SCALESHIFT		/* move PSL_IS[26] to bit 29 */
 	bl	pte_load
+	FRAME_TLBMISSUNLOCK
 	mtlr	%r29				/* restore LR */
 	/*
 	 * If we returned, pte load failed so let trap deal with it but
@@ -764,6 +812,9 @@
 	addic	%r31, %r31, 1
 	addze	%r30, %r30
 	stmw	%r30, CI_EV_TLBMISS_SOFT(%r2)
+
+	FRAME_TLBMISSUNLOCK
+
 	/*
 	 * Cleanup and leave.  We know any higher priority exception will
 	 * save and restore SPRG1 and %r2 thereby preserving their values.
Index: sys/arch/powerpc/include/booke/pmap.h
===================================================================
RCS file: /cvsroot/src/sys/arch/powerpc/include/booke/pmap.h,v
retrieving revision 1.14
diff -u -r1.14 pmap.h
--- sys/arch/powerpc/include/booke/pmap.h	3 Apr 2014 13:55:34 -0000	1.14
+++ sys/arch/powerpc/include/booke/pmap.h	23 Jan 2015 09:08:03 -0000
@@ -92,6 +92,12 @@
 
 bool	pmap_md_tlb_check_entry(void *, vaddr_t, tlb_asid_t, pt_entry_t);
 
+#ifdef MULTIPROCESSOR
+#define	PMAP_MD_NEED_TLB_MISS_LOCK
+void	pmap_md_tlb_miss_lock_enter(void);
+void	pmap_md_tlb_miss_lock_exit(void);
+#endif	/* MULTIPROCESSOR */
+
 #ifdef PMAP_MINIMALTLB
 vaddr_t	pmap_kvptefill(vaddr_t, vaddr_t, pt_entry_t);
 #endif
Index: sys/uvm/pmap/pmap.c
===================================================================
RCS file: /cvsroot/src/sys/uvm/pmap/pmap.c,v
retrieving revision 1.9
diff -u -r1.9 pmap.c
--- sys/uvm/pmap/pmap.c	5 Jan 2015 05:35:18 -0000	1.9
+++ sys/uvm/pmap/pmap.c	23 Jan 2015 09:08:03 -0000
@@ -263,6 +263,11 @@
 #define	pmap_pv_alloc()		pool_get(&pmap_pv_pool, PR_NOWAIT)
 #define	pmap_pv_free(pv)	pool_put(&pmap_pv_pool, (pv))
 
+#if !defined(MULTIPROCESSOR) || !defined(PMAP_MD_NEED_TLB_MISS_LOCK)
+#define	pmap_md_tlb_miss_lock_enter()	do { } while(/*CONSTCOND*/0)
+#define	pmap_md_tlb_miss_lock_exit()	do { } while(/*CONSTCOND*/0)
+#endif	/* !MULTIPROCESSOR || !PMAP_MD_NEED_TLB_MISS_LOCK */
+
 /*
  * Misc. functions.
  */
@@ -541,8 +546,10 @@
 	KASSERT(pmap->pm_count == 0);
 	PMAP_COUNT(destroy);
 	kpreempt_disable();
+	pmap_md_tlb_miss_lock_enter();
 	pmap_tlb_asid_release_all(pmap);
 	pmap_segtab_destroy(pmap, NULL, 0);
+	pmap_md_tlb_miss_lock_exit();
 
 #ifdef MULTIPROCESSOR
 	kcpuset_destroy(pmap->pm_active);
@@ -586,10 +593,12 @@
 	PMAP_COUNT(activate);
 
 	kpreempt_disable();
+	pmap_md_tlb_miss_lock_enter();
 	pmap_tlb_asid_acquire(pmap, l);
 	if (l == curlwp) {
 		pmap_segtab_activate(pmap, l);
 	}
+	pmap_md_tlb_miss_lock_exit();
 	kpreempt_enable();
 
 	UVMHIST_LOG(pmaphist, "<- done", 0,0,0,0);
@@ -608,8 +617,10 @@
 	PMAP_COUNT(deactivate);
 
 	kpreempt_disable();
+	pmap_md_tlb_miss_lock_enter();
 	curcpu()->ci_pmap_user_segtab = PMAP_INVALID_SEGTAB_ADDRESS;
 	pmap_tlb_asid_deactivate(pmap);
+	pmap_md_tlb_miss_lock_exit();
 	kpreempt_enable();
 
 	UVMHIST_LOG(pmaphist, "<- done", 0,0,0,0);
@@ -629,6 +640,7 @@
 	if (pending && pmap_tlb_shootdown_bystanders(pmap))
 		PMAP_COUNT(shootdown_ipis);
 #endif
+	pmap_md_tlb_miss_lock_enter();
 #ifdef DEBUG
 	pmap_tlb_check(pmap, pmap_md_tlb_check_entry);
 #endif /* DEBUG */
@@ -642,6 +654,7 @@
 		pmap_tlb_asid_acquire(pmap, curlwp);
 		pmap_segtab_activate(pmap, curlwp);
 	}
+	pmap_md_tlb_miss_lock_exit();
 	kpreempt_enable();
 
 	UVMHIST_LOG(pmaphist, "<- done", 0,0,0,0);
@@ -685,11 +698,13 @@
 			pmap_remove_pv(pmap, sva, pg,
 			   pte_modified_p(pt_entry));
 		}
+		pmap_md_tlb_miss_lock_enter();
 		*ptep = npte;
 		/*
 		 * Flush the TLB for the given address.
 		 */
 		pmap_tlb_invalidate_addr(pmap, sva);
+		pmap_md_tlb_miss_lock_exit();
 	}
 	return false;
 }
@@ -843,12 +858,14 @@
 		}
 		pt_entry = pte_prot_downgrade(pt_entry, prot);
 		if (*ptep != pt_entry) {
+			pmap_md_tlb_miss_lock_enter();
 			*ptep = pt_entry;
 			/*
 			 * Update the TLB if needed.
 			 */
 			pmap_tlb_update_addr(pmap, sva, pt_entry,
 			    PMAP_TLB_NEED_IPI);
+			pmap_md_tlb_miss_lock_exit();
 		}
 	}
 	return false;
@@ -937,9 +954,11 @@
 		pt_entry_t pt_entry = *ptep;
 		if (pte_valid_p(pt_entry)) {
 			pt_entry = pte_cached_change(pt_entry, cached);
+			pmap_md_tlb_miss_lock_enter();
 			*ptep = pt_entry;
 			pmap_tlb_update_addr(pmap, va, pt_entry,
 			    PMAP_TLB_NEED_IPI);
+			pmap_md_tlb_miss_lock_exit();
 		}
 	}
 	UVMHIST_LOG(pmaphist, "<- done", 0,0,0,0);
@@ -1060,11 +1079,13 @@
 	bool resident = pte_valid_p(opte);
 	if (!resident)
 		pmap->pm_stats.resident_count++;
+	pmap_md_tlb_miss_lock_enter();
 	*ptep = npte;
 
 	pmap_tlb_update_addr(pmap, va, npte,
 	    ((flags & VM_PROT_ALL) ? PMAP_TLB_INSERT : 0)
 	    | (resident ? PMAP_TLB_NEED_IPI : 0));
+	pmap_md_tlb_miss_lock_exit();
 	kpreempt_enable();
 
 	if (pg != NULL && (prot == (VM_PROT_READ | VM_PROT_EXECUTE))) {
@@ -1138,12 +1159,14 @@
 	pt_entry_t * const ptep = pmap_pte_reserve(pmap_kernel(), va, 0);
 	KASSERT(ptep != NULL);
 	KASSERT(!pte_valid_p(*ptep));
+	pmap_md_tlb_miss_lock_enter();
 	*ptep = npte;
 	/*
 	 * We have the option to force this mapping into the TLB but we
 	 * don't.  Instead let the next reference to the page do it.
 	 */
 	pmap_tlb_update_addr(pmap_kernel(), va, npte, 0);
+	pmap_md_tlb_miss_lock_exit();
 	kpreempt_enable();
 #if DEBUG > 1
 	for (u_int i = 0; i < PAGE_SIZE / sizeof(long); i++) {
@@ -1179,8 +1202,10 @@
 		if (pg != NULL)
 			pmap_md_vca_clean(pg, sva, PMAP_WBINV);
 
+		pmap_md_tlb_miss_lock_enter();
 		*ptep = new_pt_entry;
 		pmap_tlb_invalidate_addr(pmap_kernel(), sva);
+		pmap_md_tlb_miss_lock_exit();
 	}
 
 	return false;
@@ -1213,8 +1238,10 @@
 	 * Free all of our ASIDs which means we can skip doing all the
 	 * tlb_invalidate_addrs().
 	 */
+	pmap_md_tlb_miss_lock_enter();
 	pmap_tlb_asid_deactivate(pmap);
 	pmap_tlb_asid_release_all(pmap);
+	pmap_md_tlb_miss_lock_exit();
 	pmap->pm_flags |= PMAP_DEFERRED_ACTIVATE;
 
 	kpreempt_enable();
@@ -1258,7 +1285,9 @@
 #endif
 
 	if (pte_wired_p(pt_entry)) {
+		pmap_md_tlb_miss_lock_enter();
 		*ptep = pte_unwire_entry(*ptep);
+		pmap_md_tlb_miss_lock_exit();
 		pmap->pm_stats.wired_count--;
 	}
 #ifdef DIAGNOSTIC
@@ -1421,9 +1450,11 @@
 			continue;
 		}
 		pmap_md_vca_clean(pg, va, PMAP_WBINV);
+		pmap_md_tlb_miss_lock_enter();
 		*ptep = pt_entry;
 		VM_PAGEMD_PVLIST_UNLOCK(mdpg);
 		pmap_tlb_invalidate_addr(pmap, va);
+		pmap_md_tlb_miss_lock_exit();
 		pmap_update(pmap);
 		if (__predict_false(gen != VM_PAGEMD_PVLIST_LOCK(mdpg, false))) {
 			/*

U-Boot 2011.09-rc1-02143-g5b92c1c-dirty (Apr 27 2012 - 15:03:32)

CPU0:  P1025E, Version: 1.1, (0x80ec0311)
Core:  E500, Version: 5.1, (0x80212051)
Clock Configuration:
       CPU0:533.333 MHz, CPU1:533.333 MHz, 
       CCB:266.667 MHz,
       DDR:333.333 MHz (666.667 MT/s data rate) (Asynchronous), LBC:66.667 MHz
       QE:266.667 MHz
L1:    D-cache 32 kB enabled
       I-cache 32 kB enabled
Board: TWR-P1025 
I2C:   ready
SPI:   ready
DRAM:  Configuring DDR for 666.667 MT/s data rate
512 MiB (DDR3, 32-bit, CL=6, ECC off)
Flash: 64 MiB
L2:    256 KB enabled
MMC:  FSL_ESDHC: 0
Not a microcode
PCIe1: Root Complex of mini PCIe SLOT, no link, regs @ 0xffe0a000
PCIe1: Bus 00 - 00
PCIe2: Root Complex of TWR-ELEV PCIe SLOT, no link, regs @ 0xffe09000
PCIe2: Bus 01 - 01
In:    serial
Out:   serial
Err:   serial
Net:   eTSEC1 [PRIME], eTSEC3
Hit any key to stop autoboot: 10  0 
=> tftpboot
eTSEC1 Waiting for PHY auto negotiation to complete. done
Speed: 1000, full duplex
Using eTSEC1 device
TFTP from server 192.168.1.254; our IP address is 192.168.1.50
Filename 'uImage'.
Load address: 0x1000000
Loading: *#################################################################
	 #################################################################
	 ################
done
Bytes transferred = 2138703 (20a24f hex)
=> bootm
## Booting kernel from Legacy Image at 01000000 ...
   Image Name:   NetBSD/evbppc 7.99.4 (TWRP1025.
   Image Type:   PowerPC NetBSD Kernel Image (gzip compressed)
   Data Size:    2138639 Bytes = 2 MiB
   Load Address: 00020000
   Entry Point:  00020000
   Verifying Checksum ... OK
   Uncompressing Kernel Image ... OK
## Transferring control to NetBSD stage-2 loader (at address 00020000) ...
 initppc(0x20000, 0x4c7000, 0x1fe2dfbc, 0x0, 0x1ff8068c, 0x1fe31a10)<enter> cmdline=<root=/dev/mtdblock0 rw console=ttyS0,115200 init=/etc/preinit cache-sram-size=0x10000 cache-sram-offset=0xfff00000> root=root=/dev/mtdbl porpllsr=0x44441448 sys_clk=66666667 comcnfreq=266666668 openpic-reset(ctpr=15) cache(DC=32KB/32,IC=32KB/32) bptr=8001ffff memprobe=512MB e500_tlbinit(0x4c7000,512MB) hid0=0x80004000/0x80804000 hid1=0x44003040 pordevsr=0xa710847 devdisr=0x12480000 msgbuf=0x1fffd000 exception_init=0x356ba8 kv_nsegtabs=0x38 kv_segtabs=0x4c7000 uvm_page_physload(0x4ff,0x1fffc,0x4ff,0x1fffc,0)powerpc_fixup_stubs: 993 fixups done in 784013 cycles
 initppc done!
Loaded initial symtab at 0x4365b0, strtab at 0x466da0, # entries 12397
Copyright (c) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005,
    2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013, 2014, 2015
    The NetBSD Foundation, Inc.  All rights reserved.
Copyright (c) 1982, 1986, 1989, 1991, 1993
    The Regents of the University of California.  All rights reserved.

NetBSD 7.99.4 (TWRP1025-$Revision: 1.19 $) #4: Fri Jan 23 18:05:53 JST 2015
	nonaka@netbsd:/home/snapshot/NetBSD/20150123/obj/evbppc/sys/arch/evbppc/compile/TWRP1025.MP
total memory = 512 MB
avail memory = 497 MB
Found MP boot page @ 0x1ffff000. Spin-up table @ 0x1ffff280
mainbus0 (root)
cpunode0 at mainbus0 node 0
cpunode0: 256KB/32B 4-banked 8-way unified L2 cache
cpu0 at cpunode0 instance 1
cpu0: 533 MHz P1025E 1.1 with an e500v2 5.1 core, ID 0 (Primary)
cpu0: 32KB/32B 8-way L1 data cache
cpu0: 32KB/32B 8-way L1 instruction cache
cpu0: 2 TLBs, 3 concurrent 8-bit PIDs (256 total)
cpu0: tlb0: 512 fixed-size (4KB) 4-way set associative entries
cpu0: tlb1: 16 variable-size (4KB..4GB) fully associative entries
cpu1 at cpunode0 instance 2
e500_cpu_spinup: cpu1: entry#1(0x1ffff2a0): pir=1
e500_cpu_spinup: cpu1 set to running
e500_cpu_spinup: tb synced: offset=-148693560 (running=13)
cpu1: 533 MHz P1025E 1.1 with an e500v2 5.1 core, ID 1
cpu1: 32KB/32B 8-way L1 data cache
cpu1: 32KB/32B 8-way L1 instruction cache
cpu1: 2 TLBs, 3 concurrent 8-bit PIDs (256 total)
cpu1: tlb0: 512 fixed-size (4KB) 4-way set associative entries
cpu1: tlb1: 16 variable-size (4KB..4GB) fully associative entries
cpu1: hatch successful (24193 spins, timebase adjusted by -148693560)
e500wdog0 at cpunode0: default period is 9 seconds (wdog is active)
duart0 at cpunode0: 2 ports
com0 at duart0 port 1: ns16550a, working fifo
com0: console
com1 at duart0 port 2: ns16550a, working fifo
duart0: interrupting on irq 26
mdio0 at cpunode0 instance 1
tsec0 at cpunode0 instance 1 mdio 0 phy 2
tsec0: Ethernet address XX:XX:XX:XX:XX:XX
atphy0 at mdio0 phy 2: Atheros AR8035 10/100/1000 PHY, rev. 2
atphy0: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, 1000baseSX-FDX, 1000baseT-FDX, auto
mdio at cpunode0 instance 2 not configured
tsec at cpunode0 instance 2 not configured
mdio at cpunode0 instance 3 not configured
tsec1 at cpunode0 instance 3 mdio 0 phy 1
tsec1: Ethernet address XX:XX:XX:XX:XX:XX
atphy1 at mdio0 phy 1: Atheros AR8035 10/100/1000 PHY, rev. 2
atphy1: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, 1000baseSX-FDX, 1000baseT-FDX, auto
diic0 at cpunode0: 2 ports
iic0 at diic0: I2C bus
iic1 at diic0: I2C bus
diic0: interrupting on irq 27
gpio at cpunode0 not configured
ddrc0 at cpunode0: ECC disabled
obio0 at cpunode0: 2 of 8 ports enabled
obio0: cs0: 64MB 16-bit GPCM region at 0xec000000
obio0: cs2: 1MB 16-bit GPCM region at 0xe0000000
cfi0 at obio0 cs 0 addr 0xec000000 size 0x4000000
cfi0: CFI NOR flash 64 MB x8/x16
nor0 at cfi0
nor0: page size: 64, spare size: 0, block size: 128 KB
nor0: LUN size: 512 blocks, LUNs: 1, total storage size: 64 MB
flash0 at nor0: NOR flash partition size 64 MB, offset 0
flash0: erase size 128 KB bytes, write size 64 bytes
pq3pcie0 at cpunode0 instance 1: PCI-Express x1 controller
pci0 at pq3pcie0 bus 0
ppb0 at pci0 dev 0 function 0: Freescale Semiconductor P1025E (rev. 0x11)
ppb0: not configured by system firmware
pq3pcie1 at cpunode0 instance 2: PCI-Express x1 controller
pci1 at pq3pcie1 bus 0
ppb1 at pci1 dev 0 function 0: Freescale Semiconductor P1025E (rev. 0x11)
ppb1: not configured by system firmware
ehci0 at cpunode0 instance 1: USB controller
ehci0: interrupting on irq 12
usb0 at ehci0: USB revision 2.0
spi at cpunode0 not configured
sdhc0 at cpunode0: SDHC controller
sdhc0: interrupting on irq 56
sdhc0: SD Host Specification 1.0, rev.0
sdmmc0 at sdhc0 slot 0
cpunode0: gpio[a]: 32 input/output/opendrain pins
gpio0 at cpunode0: 32 pins
cpunode0: gpio[b]: 31 input/output/opendrain pins
gpio1 at cpunode0: 32 pins
cpunode0: gpio[c]: 32 input/output/opendrain pins
gpio2 at cpunode0: 32 pins
WARNING: module error: vfs load failed for `usbverbose', error 45
uhub0 at usb0WARNING: module error: vfs load failed for `usbverbose', error 45
: vendor 0000 EHCI root hub, class 9/0, rev 2.00/1.00, addr 1
ld0 at sdmmc0: <0x03:0x5344:SU04G:0x80:0x03a8aa97:0x0c9>
ld0: 3781 MB, 1920 cyl, 64 head, 63 sec, 512 bytes/sect x 7744512 sectors
ld0: 4-bit width, bus clock 50.000 MHz
WARNING: module error: vfs load failed for `usbverbose', error 45
uhub1 at uhub0 port 1WARNING: module error: vfs load failed for `usbverbose', error 45
: vendor 05e3 USB2.0 Hub, class 9/0, rev 2.00/77.63, addr 2
uhub1: single transaction translator
root on tsec0
nfs_boot: trying DHCP/BOOTP
tsec0: link state UP (was UNKNOWN)
nfs_boot: DHCP next-server: 192.168.1.254
nfs_boot: my_addr=192.168.1.50
nfs_boot: my_mask=255.255.255.0
nfs_boot: gateway=192.168.1.254
root on 192.168.1.254:/exports/nfsroot/TWR-P1025/root
root time: 0x54c20f4a
kern.module.path=/stand/powerpc-booke/7.99.4/modules
WARNING: no TOD clock present
WARNING: using filesystem time
WARNING: CHECK AND RESET THE DATE!
init: copying out path `/sbin/init' 11
Fri Jan 23 18:07:22 JST 2015
Not checking /: fs_passno = 0 in /etc/fstab
Starting file system checks:
random_seed: /var/db/entropy-file: Not present
Setting tty flags.
Setting sysctl variables:
ddb.onpanic: 1 -> 0
Starting network.
Hostname: twr-p1025
IPv6 mode: host
Configuring network interfaces:.
Adding interface aliases:.
add net default: gateway 192.168.1.254
Waiting for DAD to complete for statically configured addresses...
Building databases: dev, utmp, utmpx.
Starting syslogd.
Setting date via ntp.
Starting rpcbind.
Mounting all file systems...
Clearing temporary files.
Checking quotas: done.
Starting statd.
Starting lockd.
Setting securelevel: kern.securelevel: 0 -> 1
swapctl: adding netbsd:/exports/nfsroot/TWR-P1025/swap as swap device at priority 0
Starting virecover.
Checking for core dump...
savecore: no core dump (no dumpdev)
Starting local daemons:.
Updating motd.
Starting sshd.
Starting inetd.
Starting cron.
Fri Jan 23 18:08:22 JST 2015

NetBSD/evbppc (twr-p1025) (console)

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