Re: OpenPIC and sandpoint

Kiyohara asked about OpenPIC code;

> The OpenPIC always set OPENPIC_POLARITY_POSITIVE, if the variable irq == 0
> in arch/powerpc/pic/pic_openpic.c::opic_establish_irq().
>
>        x = irq;
>        x |= OPENPIC_IMASK;
>        x |= (irq == 0) ?
>            OPENPIC_POLARITY_POSITIVE : OPENPIC_POLARITY_NEGATIVE;
>        x |= (type == IST_EDGE) ? OPENPIC_SENSE_EDGE : OPENPIC_SENSE_LEVEL;
>        :
>        openpic_write(OPENPIC_SRC_VECTOR(irq), x);

It's a historical implication about "OpenPIC standard" and its implementation variations.

(disclaimer; my knowledge is limited around Moto/Freescale MPC interrupt controller
and I have no clue about IBM / Apple implementations)

IRQ0 odd case is derived from the fact the IRQ input line used to be specifically wired
for i8259 ISA style interrupt controller.  Moto's "extened OpenPIC standard" interrupt
controllers allow a mode selection among "i8259 wiring (stands for original OpenPIC
specification)" and "straight wiring" mode.  Documentations, somehow confusingly,
call them "pass through mode" and "mixed mode".  One particular bit in Gobal
Configuration Register, GCR[M] bit, specifies the difference to tell how the target HW
is wired.

Many NAS boxes like Kurobox or others have no PCI+ISA south-bridge inside and is
free from nasty i8259 handling.  GCR[M] bit is programmed 1, "mixed mode," to reflect
this design, and it means positive for IRQ0 makes no sense.

You should grab PDFs and search key words, "mixed mode" and/or "pass through
mode," to spot the definition and explaination.  And then come back to NetBSD
openpic.c implementation to seek the solution for this particular issue in a concise
and smart way.  I'm uncertain whether your proposed solution could go beyond
one-time hack which just makes sense for MPC8245 to differentiate it from other
OpenPIC compliants.

Toru Nishimura / ALKYL Technology