Re: mec and resets

On Sat, Aug 02, 2008 at 03:11:04PM +0900, Izumi Tsutsui wrote:
> This is an updated one (mostly taken from OpenBSD):

This (and actually the version before too) make it work for me on
both machines:

cpu0 at mainbus0: MIPS R10000 CPU (0x926) Rev. 2.6 with built-in FPU Rev. 0.0
cpu0: 32KB/64B 2-way set-associative L1 Instruction cache, 64 TLB entries    
cpu0: 32KB/32B 2-way set-associative write-back L1 Data cache            
cpu0: 1024KB/64B 2-way set-associative write-back L2 Data cache

and:

cpu0 at mainbus0: MIPS R5000 CPU (0x2321) Rev. 2.1 with built-in FPU Rev. 1.0
cpu0: 32KB/32B 2-way set-associative L1 Instruction cache, 48 TLB entries
cpu0: 32KB/32B 2-way set-associative write-back L1 Data cache
cpu0: 1024KB/32B direct-mapped write-through L2 Unified cache

Great!

The only open issue with the R10k machine now seems to be the clock -
it runs in a completely different dimension:

mips int 5 (clock)                            40163      208 intr

while on the R5k it interrupts at 100Hz as expected.

Martin