Re: landisk DMA broken in NetBSD 6

> > Can you try reverting revision 1.15 (1.14.8.1 on netbsd-6):
> >
> > revision 1.14.8.1
> > date: 2012-04-06 21:28:04 +0400;  author: riz;  state: Exp;  lines: +2 -7;
> > Pull up following revision(s) (requested by tsutsui in ticket #160):
> > 	sys/arch/landisk/landisk/bus_dma.c: revision 1.15
> > Don't call sh_dcache_inv_range() on BUS_DMASYNC_POSTREAD ops
> > as other mips and arm ports.
> > All cached data is cared on BUS_DMASYNC_PREREAD and
> > invalidating cache without writeback could cause unexpected
> > data loss if specified sync region is not cacheline aligned.
> > This may fix "ffs_alloccg: map corrupted" panic on acardide IDE disks,
> > which didn't happen on USB HDD.
> 
> I did this several days ago and have run tons of stuff since - cvs 
> updates, pkg_rolling-replace, et cetera, and have had no problems. That 
> definitely fixed the issue.

Well I doubt it fixes the problem..

As noted in the log, the FFS corruption also happened before the commit
and invalidate on POSTREAD might cause data loss on writeback systems
(though current landisk seems to use writethrough).

If it really changes your problem, there are other bugs around cache ops
and the invalidate op hides the actual problem.

Could you also try sys/arch/sh3/sh3/cache_sh4.c rev 1.21-1.24
http://cvsweb.netbsd.org/bsdweb.cgi/src/sys/arch/sh3/sh3/cache_sh4.c?only_with_tag=MAIN
and the following diff?

--- cache_sh4.c.orig
+++ cache_sh4.c	2013-06-02 17:55:00.000000000 +0900
@@ -77,6 +77,7 @@
 	int dcache_size;
 	int ways;
 	uint32_t r;
+	bool have_emode = false;
 
         /* Determine cache size */
 	switch (cpu_product) {
@@ -85,25 +86,27 @@
 	case CPU_PRODUCT_7750:
 	case CPU_PRODUCT_7750S:
 	case CPU_PRODUCT_7751:
-#if defined(SH4_CACHE_DISABLE_EMODE)
-	case CPU_PRODUCT_7750R:
-	case CPU_PRODUCT_7751R:
-#endif
 		icache_size = SH4_ICACHE_SIZE;
 		dcache_size = SH4_DCACHE_SIZE;
 		ways = 1;
 		r = SH4_CCR_ICE|SH4_CCR_OCE|SH4_CCR_WT;
 		break;
 
-#if !defined(SH4_CACHE_DISABLE_EMODE)
 	case CPU_PRODUCT_7750R:
 	case CPU_PRODUCT_7751R:
+#if !defined(SH4_CACHE_DISABLE_EMODE)
 		icache_size = SH4_EMODE_ICACHE_SIZE;
 		dcache_size = SH4_EMODE_DCACHE_SIZE;
 		ways = 2;
 		r = SH4_CCR_EMODE|SH4_CCR_ICE|SH4_CCR_OCE|SH4_CCR_WT;
-		break;
+#else
+		icache_size = SH4_ICACHE_SIZE;
+		dcache_size = SH4_DCACHE_SIZE;
+		ways = 1;
+		r = SH4_CCR_ICE|SH4_CCR_OCE|SH4_CCR_WT;
 #endif
+		have_emode = true;
+		break;
 	}
 #if defined(SH4_CACHE_DISABLE_ICACHE)
 	r &= ~SH4_CCR_ICE;
@@ -119,7 +122,7 @@
 #endif
 
 	RUN_P2;
-	if (r & SH4_CCR_EMODE)
+	if (have_emode)
 		SH4_EMODE_CACHE_FLUSH();
 	else
 		SH4_CACHE_FLUSH();

---
Izumi Tsutsui