adding macro to set/clr bits for devreg

I'd like to add macro in sh3/include/devreg.h to set/clear
bits in embeded device registers for readability.
(patch attached)

Any comments/objections?
---
Izumi Tsutsui
[email protected]

Index: include/devreg.h
===================================================================
RCS file: /cvsroot/syssrc/sys/arch/sh3/include/devreg.h,v
retrieving revision 1.2
diff -u -r1.2 devreg.h
--- include/devreg.h	2002/04/28 17:10:34	1.2
+++ include/devreg.h	2002/11/04 03:33:58
@@ -46,11 +46,23 @@
 #define	_reg_read_2(a)		(*(__volatile__ u_int16_t *)((vaddr_t)(a)))
 #define	_reg_read_4(a)		(*(__volatile__ u_int32_t *)((vaddr_t)(a)))
 #define	_reg_write_1(a, v)						\
-	(*(__volatile__ u_int8_t *)(a) = (u_int8_t)(v))
+	(*(__volatile__ u_int8_t *)(a)  = (u_int8_t)(v))
 #define	_reg_write_2(a, v)						\
 	(*(__volatile__ u_int16_t *)(a) = (u_int16_t)(v))
 #define	_reg_write_4(a, v)						\
 	(*(__volatile__ u_int32_t *)(a) = (u_int32_t)(v))
+#define	_reg_bset_1(a, v)						\
+	(*(__volatile__ u_int8_t *)(a)  |= (u_int8_t)(v))
+#define	_reg_bset_2(a, v)						\
+	(*(__volatile__ u_int16_t *)(a) |= (u_int16_t)(v))
+#define	_reg_bset_4(a, v)						\
+	(*(__volatile__ u_int32_t *)(a) |= (u_int32_t)(v))
+#define	_reg_bclr_1(a, v)						\
+	(*(__volatile__ u_int8_t *)(a)  &= (u_int8_t)~(v))
+#define	_reg_bclr_2(a, v)						\
+	(*(__volatile__ u_int16_t *)(a) &= (u_int16_t)~(v))
+#define	_reg_bclr_4(a, v)						\
+	(*(__volatile__ u_int32_t *)(a) &= (u_int32_t)~(v))
 
 /*
  * Register address.
Index: sh3/cache_sh3.c
===================================================================
RCS file: /cvsroot/syssrc/sys/arch/sh3/sh3/cache_sh3.c,v
retrieving revision 1.6
diff -u -r1.6 cache_sh3.c
--- sh3/cache_sh3.c	2002/05/10 15:28:45	1.6
+++ sh3/cache_sh3.c	2002/11/04 03:33:59
@@ -150,7 +150,7 @@
 	/* operate for each way */
 	for (way = 0; way < n; way++) {
 		cca = (SH3_CCA | way << sh_cache_way_shift | va);
-		_reg_write_4(cca, _reg_read_4(cca) & ~bits);
+		_reg_bclr_4(cca, bits);
 	}
 }
 
Index: sh3/cache_sh4.c
===================================================================
RCS file: /cvsroot/syssrc/sys/arch/sh3/sh3/cache_sh4.c,v
retrieving revision 1.6
diff -u -r1.6 cache_sh4.c
--- sh3/cache_sh4.c	2002/05/09 12:30:11	1.6
+++ sh3/cache_sh4.c	2002/11/04 03:34:00
@@ -117,7 +117,7 @@
 	vaddr_t cca;
 
 	cca = base | (va & mask);
-	_reg_write_4(cca, _reg_read_4(cca) & ~bits);
+	_reg_bclr_4(cca, bits);
 }
 
 /*
Index: sh3/clock.c
===================================================================
RCS file: /cvsroot/syssrc/sys/arch/sh3/sh3/clock.c,v
retrieving revision 1.26
diff -u -r1.26 clock.c
--- sh3/clock.c	2002/07/18 02:10:43	1.26
+++ sh3/clock.c	2002/11/04 03:34:00
@@ -106,9 +106,9 @@
  */
 #define	TMU_START(x)							\
 do {									\
-	_reg_write_1(SH_(TSTR), _reg_read_1(SH_(TSTR)) & ~TSTR_STR##x);	\
+	_reg_bclr_1(SH_(TSTR), TSTR_STR##x);				\
 	_reg_write_4(SH_(TCNT ## x), 0xffffffff);			\
-	_reg_write_1(SH_(TSTR), _reg_read_1(SH_(TSTR)) | TSTR_STR##x);	\
+	_reg_bset_1(SH_(TSTR), TSTR_STR##x);				\
 } while (/*CONSTCOND*/0)
 #define	TMU_ELAPSED(x)							\
 	(0xffffffff - _reg_read_4(SH_(TCNT ## x)))
@@ -261,7 +261,7 @@
 	/*
 	 * Use TMU channel 0 as hard clock
 	 */
-	_reg_write_1(SH_(TSTR), _reg_read_1(SH_(TSTR)) & ~TSTR_STR0);
+	_reg_bclr_1(SH_(TSTR), TSTR_STR0);
 
 	if (sh_clock.flags & SH_CLOCK_NORTC) {
 		/* use PCLOCK/16 as TMU0 source */
@@ -279,7 +279,7 @@
 	intc_intr_establish(SH_INTEVT_TMU0_TUNI0, IST_LEVEL, IPL_CLOCK,
 	    CPU_IS_SH3 ? sh3_clock_intr : sh4_clock_intr, 0);
 	/* start hardclock */
-	_reg_write_1(SH_(TSTR), _reg_read_1(SH_(TSTR)) | TSTR_STR0);
+	_reg_bset_1(SH_(TSTR), TSTR_STR0);
 
 	/*
 	 * TMU channel 1, 2 are one shot timer.
@@ -375,7 +375,7 @@
 	wdog_wr_cnt(0);			/* reset to zero */
 #endif
 	/* clear underflow status */
-	_reg_write_2(SH3_TCR0, _reg_read_2(SH3_TCR0) & ~TCR_UNF);
+	_reg_bclr_2(SH3_TCR0, TCR_UNF);
 
 	hardclock(arg);
 
@@ -395,7 +395,7 @@
 	wdog_wr_cnt(0);			/* reset to zero */
 #endif
 	/* clear underflow status */
-	_reg_write_2(SH4_TCR0, _reg_read_2(SH4_TCR0) & ~TCR_UNF);
+	_reg_bclr_2(SH4_TCR0, TCR_UNF);
 
 	hardclock(arg);
 
@@ -421,7 +421,7 @@
 	int retry = 8;
 
 	/* disable carry interrupt */
-	_reg_write_1(SH_(RCR1), _reg_read_1(SH_(RCR1)) & ~SH_RCR1_CIE);
+	_reg_bclr_1(SH_(RCR1), SH_RCR1_CIE);
 
 	do {
 		u_int8_t r = _reg_read_1(SH_(RCR1));
Index: sh3/db_interface.c
===================================================================
RCS file: /cvsroot/syssrc/sys/arch/sh3/sh3/db_interface.c,v
retrieving revision 1.19
diff -u -r1.19 db_interface.c
--- sh3/db_interface.c	2002/05/13 20:30:10	1.19
+++ sh3/db_interface.c	2002/11/04 03:34:02
@@ -433,7 +433,7 @@
 	}
 
 	/* enable cache */
-	_reg_write_4(SH3_CCR, _reg_read_4(SH3_CCR) | SH3_CCR_CE);
+	_reg_bset_4(SH3_CCR, SH3_CCR_CE);
 	sh_icache_sync_all();
 
 	RUN_P1;
Index: sh3/interrupt.c
===================================================================
RCS file: /cvsroot/syssrc/sys/arch/sh3/sh3/interrupt.c,v
retrieving revision 1.3
diff -u -r1.3 interrupt.c
--- sh3/interrupt.c	2002/09/27 15:36:42	1.3
+++ sh3/interrupt.c	2002/11/04 03:34:03
@@ -394,15 +394,15 @@
 {
 
 	_reg_write_4(SH_(TCNT1), 0);
-	_reg_write_1(SH_(TSTR), _reg_read_1(SH_(TSTR)) | TSTR_STR1);
+	_reg_bset_1(SH_(TSTR), TSTR_STR1);
 }
 
 int
 tmu1_intr(void *arg)
 {
 
-	_reg_write_1(SH_(TSTR), _reg_read_1(SH_(TSTR)) & ~TSTR_STR1);
-	_reg_write_2(SH_(TCR1), _reg_read_2(SH_(TCR1)) & ~TCR_UNF);
+	_reg_bclr_1(SH_(TSTR), TSTR_STR1);
+	_reg_bclr_2(SH_(TCR1), TCR_UNF);
 
 	softintr_dispatch(IPL_SOFTCLOCK);
 	softintr_dispatch(IPL_SOFT);
@@ -415,15 +415,15 @@
 {
 
 	_reg_write_4(SH_(TCNT2), 0);
-	_reg_write_1(SH_(TSTR), _reg_read_1(SH_(TSTR)) | TSTR_STR2);
+	_reg_bset_1(SH_(TSTR), TSTR_STR2);
 }
 
 int
 tmu2_intr(void *arg)
 {
 
-	_reg_write_1(SH_(TSTR), _reg_read_1(SH_(TSTR)) & ~TSTR_STR2);
-	_reg_write_2(SH_(TCR2), _reg_read_2(SH_(TCR2)) & ~TCR_UNF);
+	_reg_bclr_1(SH_(TSTR), TSTR_STR2);
+	_reg_bclr_2(SH_(TCR2), TCR_UNF);
 
 	softintr_dispatch(IPL_SOFTSERIAL);
 	softintr_dispatch(IPL_SOFTNET);