Re: SPARCStation VSIMM

Le jeu. 28 oct. 2021 à 20:58, Michael <[email protected]> a écrit :
> That said, the suncg14 driver in -current supports a good part of the
> most common xrender operations ( basically, what's needed to render
> anti-aliased text and images with transparency ), it's disabled by
> default since there aren't many people testing it. Options "xrender"
> "true" will enable it.

Very interesting ; so basically if you have some sort of sufficiently
programmable core to deal with acceleration, you can do Xrender?
I'm guessing from 'transparency' you also presumably need 24+ bits
TrueColor, not some 8-bits indexed mode?
Do you need FP, or is integer enough?

My current cg6 re-implementation [1] is basically a small RV32 core
[2] and some microcode to implement the functionalities used by the
PROM console and NetBSD (console and X11).
It's not particularly fast, but as a proof-of-concept it seems to be working.
It could be used for a 24/32-bits framebuffer PoC easily.
(it has an optional FPU in SP or SP/DP but that adds a lot of area to the core).

An alternative I've considered would be to leverage Betrusted's
Curve25519 crypto engine [3], it's basically a 50 Mhz instruction
sequencer that can do 100 Mhz execution for multi-cycle instructions,
with a wide (32x256 bits by default) register file (running at 200 MHz
to get data fast enough);
I've already added a simple Wishbone Load/Store unit to implement
AES256 and GHASH (for the full GCM mode) in it directly out of a DVMA
buffer.
It's quite versatile, so using narrower registers and SIMD-like
instructions would be very doable.
The primary issue would be unaligned memory accesses; it seems to
always be the issue...

Cordially,

Romain

[1] <https://github.com/rdolbeau/SBusFPGA>
[1] a fairly basic VexRiscv with some useful instructions from
B[itmanip] such as byte reversal, ternary operations cmix/cmov,
sh[123]add for address computations, ...
[2] <https://www.bunniestudios.com/blog/?p=6140>

-- 
Romain Dolbeau