Re: New Timekeeper/RAM clock stops on power loss?
Mouse <[email protected]> Thu, 3 Jul 2025 07:44:21 -0400 (EDT)
| Newsgroups | gmane.os.netbsd.ports.sparc |
|---|---|
| Message-ID | <[email protected]> |
>> On this particular machine (or maybe just this particular part), >> when the power is lost (either by utility failure or normal >> power-down) the clock stops ticking. When powered up again, the OBP >> reports "Starting real-time clock", This sounds to me like a dead NVRAM/clock chip battery. >> as if the timekeeper/RAM had been put to sleep using "power-off" >> from OBP (sets "ST" bit in one of the clock control registers). In my experience, that's not what power-off does. power-off just turns power off, without stopping the clock chip's clock. It is possible to stop the chip's clock from OBP, but not by default as far as I can tell; nvramrc on my SPARCs includes : stop-clock f1201000 f 0 map-page 80 ff8 c! 80 ff9 c! 0 ff8 c! ; (for SS20; depending on the machine, some of the numbers may need to change). When the machine is going to be powered down more than briefly, I use that first, to preserve what battery life remains. /~\ The ASCII Mouse \ / Ribbon Campaign X Against HTML [email protected] / \ Email! 7D C8 61 52 5D E7 2D 39 4E F1 31 3E E8 B3 27 4B