Re: SPARC hardware with weaker ordering than TSO

Yes I believe so, see UltraSPARC II and IIi user's manuals

Copied verbatim:

"SPARC-V9 defines the semantics of memory operations for three memory
models. From strongest to weakest, they are Total Store Order (TSO),
Partial Store Order (PSO), and Relaxed Memory Order (RMO). The
differences in these models lie in the freedom an implementation is
allowed in order to obtain higher performance during program execution.
The purpose of the memory models is to specify any constraints placed
on the ordering of memory operations in uniprocessor and shared-memory
multi-processor environments. UltraSPARC-IIi supports all three memory
models."

and

"Block load and store operations do not obey the ordering restrictions
of the currently selected processor memory model (TSO, PSO, or RMO);
block operations always execute under an RMO memory ordering model.
Explicit MEMBAR instructions are required to order block operations
among themselves or with respect to normal loads and stores. In
addition, block operations do not conform to dependence order on the
issuing processor; that is, no read-after-write or writer-after-read
checking occurs between block loads and stores. Explicit MEMBARs are
required to enforce dependence ordering between block operations that
reference the same address."