Re: 10_BETA panic on Ultra 1

I looked at the code a bit and I don't think there is a PIL problem,
but looking at intrcmplt: in locore.s:4762 I wonder if we need to improve
the handling of CI_IDEPTH when handling multiple interrupts at the same
hardware protection level - we only decrement it once at the end of the
loop, right before restoring the previous PIL and returning.

So now I wonder if we map some softints and some hardints at the same PIL
on the affected machines (sbus interrupts being different) and this opens
the door for a race to make this assert fire - while (by plain luck) no
PIL collision happens on the PCI machines. I forgot all the details and
need to dive deeper :-/

Martin