Re: sun4v trap table

On Sun, 5 Oct 2025 09:17:48 +0200
Martin Husemann <[email protected]> wrote:

> On Sun, Oct 05, 2025 at 07:30:11AM +0100, Sad Clouds wrote:
> 
> > Does anyone know how the TT (Trap Type) maps to the table entries?
> > For example, when TT=0x080 why does the kernel think it needs to use
> > SPILL64() and for example, not SPILL32(). Where is this defined?
> 
> > The architecture manual does not seem to specify the details, so I
> > assume it is left up to the OS kernel to decide? Is this correct?
> 
> I am not sure I understand the question correctly.
> 
> All trap entries have constant size, the cpu (trivially) calculates the
> start address of the handler directly from the TT.
> 
> What kind of code we put into that slot is all up to us, it is not defined
> anywhere besides the table you quoted. But it usually should be obvious
> from the TT definition what we want the trap handler to do.
> 
> Martin

OK let me elaborate. From what I understand:

There are multiple TLs (Trap Levels) which can be nested. TL=0 is set
when occurring in unprivileged user space, TL>0 is set when occurring in
privileged (OS kernel, Hypervisor, etc) space.

NetBSD trap table has entries for TL=0 and TL>0, to run trap handlers
for either user space or kernel space. The table effectively consists
two halves. To start with, I'm just looking at TL=0 and specifically TTs
(Trap Types) starting with 0x080 which correspond to spill_N_normal,
spill_N_other, fill_N_normal, fill_N_other, where N can be 0 to 7.

So the trap table may look like:

...
0x080 spill_0_normal
0x084 spill_1_normal
0x088 spill_2_normal
... etc.

Hardware uses registers OTHERWIN and WSTATE to decided which trap
handler to execute. Below is copied verbatim from the manual:

"Supervisor software can specify the trap vectors for fill and spill
traps by presetting the fields in the WSTATE register. This register
contains two subfields, each three bits wide. The WSTATE.normal field
determines one of eight spill (fill) vectors to be used when the
register window to be spilled (filled) belongs to the current address
space (OTHERWIN = 0). If the OTHERWIN register is nonzero, the
WSTATE.other field selects one of eight fill_n_other (spill_n_other)
trap vectors."

I'm trying to understand how NetBSD kernel maps WSTATE.normal and
WSTATE.other to the TTs. It must follow some sort of convention and set
the appropriate bits in those registers at various times. Because the
mapping is completely different for NetBSD and Illumos. The trap tables
contain completely different handlers.