Re: I/O bus reset to fix CMD MSCP controllers (and probably others)

Den 2025-03-31 kl. 16:36, skrev Mouse:
>>> Data point: when I boot 1.4T under my emulator, I see only three I/O
>>> resets.  One is the emulator resetting itself during startup.  The
>>> other two are due to writes to IPR 55, which happen [in ROM code]
>> Could you see if there are any writes to the IP register?  That would
>> be the software reset of just that controller.
> I see five writes to IP, from startup to single-user shell.  In terms
> of console output, they happen:
>
> (1) After "2.." and before "1..0..".
> (2) After "0..\r\n\n" and before "\n\r\r>> NetBSD/vax boot"
> (3) After "> boot -s\r\n" and before the twirler starts.
> (4) After "uba0 at ibus0: Q22\n\r\r" and before "uda0 at uba0".
> (5) After "mscpbus0 at uda0" and before ": version 0 model 0".
We can note here that it is the same uda/mscp code here in Mouse's 
emulator (running 1.4T) as it is in the current source.
Also, the writing to IP are the same.

Something about odd controllers that I remember; I once got hold of an 
Emulex UC04 controller which I never got working, no matter what I tried.
I got the feeling that it was timing-dependent to initialize it.

BTW, Hans, have you tried fiddling with the DELAY() timer?

Also, since booting works where it will init the controller, I glanced 
at that code as well (ra.c).
It do not have any delays at all; looks more or less like this:

         *ra_ip = 0; /* Start init */

         /* Init of this uda */
         while ((*ra_sa & MP_STEP1) == 0)
                 ;
         *ra_sw = 0x8000;
         while ((*ra_sa & MP_STEP2) == 0)
                 ;
         *ra_sw = johan;
         while ((*ra_sa & MP_STEP3) == 0)
                 ;
         *ra_sw = johan2;
         while ((*ra_sa & MP_STEP4) == 0)
                 ;

-- Ragge