Re: PSA: Clock drift and pkgin

On 2023-12-19 16:20, Maciej W. Rozycki wrote:
> On Tue, 19 Dec 2023, Johnny Billquist wrote:
> 
>>>    Which is exactly why I keep writing we ought not be doing this (if we do)
>>> and should rely solely on the high-resolution timer for timekeeping.
>>
>> No real disagreement there, except if you mean something like the DS1287 then
>> I'm not sure I agree on the definition of "high resolution timer".
> 
>   The DS1287 is an example source of the timer interrupt with some systems
> where a high-resolution timer has to provided separately, just as with the
> 4000/60.  By no means I find the DS1287 itself a high-resolution timer.

Ok. Then we agree, and I'll drop that. :)

I would still think that if you have the full ICCS and ICR register in 
the VAX, it is better than such a chip, or probably any chip.

>>>    Conversely what I have been concerned with is incorrect operation with
>>> actual hardware, and then this specific one.
>>
>> Did anyone actually report results running on a 4000/60?
> 
>   Me, earlier on in this thread.

Great. Sorry that I didn't remember. How did the clock behave for you?

>   I do have a 4000/90 too, but it suffers from an issue I yet need to debug
> where it ever boots NetBSD 9 from local storage only once.  Then the OS
> corrupts itself somehow in storage such that any subsequent attempt to
> boot causes the firmware to fail:

Weird. I have a 4000/90, and have never observed such issues. But now 
it's a few months since I last spun it up. I plan to test it out with 
the current updates after christmas.

>> Personally, I've been
>> running on a 4000/90, where time is not working well. But that one would be
>> depending on the ICR. But I haven't checked if it actually do have a proper
>> ICR. Does anyone know?
> 
>   It does, implemented in the NCA.

I was reading the NVAX chip documentation, and it apparently is partly 
dependent on external support. So I tried to find specific documentation 
for the 4000/90, but didn't manage to find anything so far.

>   NB I worked with Mike Uhler (the lead designer of the NVAX in case you
> didn't know), who was the manager of our group at MIPS UK back in early
> 2000s, and knowing his absolute technical insight I'd have no doubt he
> wouldn't let such an important architectural feature out of the NVAX
> microarchitecture.

Very cool/nice. But as observed, the NVAX don't have it built in as 
such. So it might, or might not exist on a specific machine, depending 
on external bits. The NVAX itself only guarantees that the ICCS exists, 
and can generate 10ms interval interrupts, which is the basic 
requirement for any VAX. The documentation for the NVAX chip is on 
bitsavers.

   Johnny

-- 
Johnny Billquist                  || "I'm on a bus
                                   ||  on a psychedelic trip
email: [email protected]             ||  Reading murder books
pdp is alive!                     ||  tryin' to stay hip" - B. Idol