On Tue, Dec 15, 2020 at 11:39:11AM +0100, [email protected] wrote:
> Hi,
>
> On Tue, Dec 15, 2020 at 11:29:48AM +0100, Martin Husemann wrote:
> > On Tue, Dec 15, 2020 at 11:24:34AM +0100, [email protected] wrote:
> > > > Do the disks downgrade transfer modes on first access (or soonish)?
> > >
> > > no more matches.
> >
> > OK (would have been a bit of suprise for SATA disks anyway, but better to
> > check before we run off in tangents).
> >
> > Is the interrupt mapping for the piixide identical in the old and the new
> > kernel?
>
> I'll have to screenshot via the kvm to find out, but I can only try this
> if I first move at least two of the VMs away or if I'm in the building,
> not planned before Thursday.
Looks similar to me, with the exception of pci0 dev 31 function 0, which
is attached as timer now --- or is that, mentioned as having a timer?
-is
=======9.99.77========
[...]
ichlpcib0 at pci0 dev 31 function 0: vendor 8086 product 3b14 (rev.0x05)
ichlpcib0: 24 bit timer
piixide0 at pci0 dev 31 function 2: Intel 3400 Serial ATA Controler (rev. 0x05)
piixide0: using ioapic0 pin 20 for native-PCI interupt
atabus0 at piixide0 channel 0
atabus1 at piixide0 channel 1
piixide0 at pci0 dev 31 function 5: Intel 3400 Serial ATA Controler (rev. 0x05)
piixide0: using ioapic0 pin 21 for native-PCI interupt
atabus2 at piixide1 channel 0
atabus3 at piixide1 channel 1
isa0 at ichlpcib0
[...]
======== 6.1.5 ========
pcib0 at pci0 dev 31 function 0: vendor 0x8086 product 0x3b14 (rev. 0x05)
piixide0 at pci0 dev 31 function 2: Intel 3400 Serial ATA Controller (rev. 0x05)
piixide0: bus-master DMA support present
piixide0: primary channel configured to native-PCI mode
piixide0: using ioapic0 pin 20, event channel 6 for native-PCI interrupt
atabus0 at piixide0 channel 0
piixide0: secondary channel configured to native-PCI mode
atabus1 at piixide0 channel 1
piixide1 at pci0 dev 31 function 5: Intel 3400 Serial ATA Controller (rev. 0x05)
piixide1: bus-master DMA support present
piixide1: primary channel wired to native-PCI mode
piixide1: using ioapic0 pin 21, event channel 7 for native-PCI interrupt
atabus2 at piixide1 channel 0
piixide1: secondary channel wired to native-PCI mode
--
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Gemeinsame Systemgruppe b-it + Informatik Tel. +49 228 73-60701
[email protected]
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