Re: iwx 64-bit dma

On Wed, Jul 29, 2026 at 06:29:12PM -0600, Theo de Raadt wrote:
> Vitaliy Makkoveev <[email protected]> wrote:
> 
> > On Wed, Jul 29, 2026 at 04:22:51PM -0600, Theo de Raadt wrote:
> > > Are _all models_ of this chipset safe?
> > > 
> > 
> > I don't know about PCI versions of this device. Moreover, it uses 64
> > bits DMA since  revision 1.198 of sys/dev/pci/if_iwx.c.
> 
> 
> The chipset always uses 64 bit descriptors, but they always pointed
> into 32-bit memory.
> 
> There is other hardware that has 64 bit descriptors but can only access
> less than 64 bits, for example kettenis sent a mail a week ago about
> something which does 48 bits (but on a platform which has all memory
> below that line)
> 
> So we must still be certain.  The existance of 64 bit descriptors is
> not conclusive.
>  

The IFXF_MBUF_64BIT flag affects only amd64. All other architectures
still uses memory below 4G. See revision 1.61 of
sys/arch/amd64/amd64/autoconf.c line 129.

> > revision 1.198
> > date: 2026/02/17 20:02:43;  author: kettenis;  state: Exp;  lines: +8 -7;  commi
> > tid: zh15zLsr17Uwlskc;
> > Sprinkle some BUS_DMA_64BIT; this hardware has no issues handling full
> > 64-bit addresses.
> > 
> > ok stsp@
> > 
> > But later, bluhm@ introduced IFXF_MBUF_64BIT flag for interface
> > descriptor. The 64 bits DMA will not be used if at least one interface
> > was configured without this flag. It seems iwx(4) was forgotten like
> > re(4).
> > 
> > revision 1.306
> > date: 2026/06/23 14:40:40;  author: bluhm;  state: Exp;  lines: +30 -1; commiti
> > d: stkeyyILuxfbNN6W;
> > Allocate mbufs in high memory if only 64 bit DMA interfaces exist.
> > 
> > Mbufs on amd64 were allocated below 4 GB so that devices not capable
> > of 64 bit DMA can access the memory.  Interface drivers use
> > BUS_DMA_64BIT to allow the DMA layer doing 64 bit transfers.  Now
> > flag interfaces with IFXF_MBUF_64BIT that are capable of 64 bit DMA
> > on all their mbuf rings.
> > 
> > If only such interfaces exist in the system during amd64 boot,
> > allocate mbufs and mbuf clusters also in high memory.  Other
> > architectures may be limited to 32 bit memory anyway or use an
> > IOMMU.  On riscv64 or arm64 busses may exists that support less
> > than 64 bit, this will be handled later.
> > 
> > Hotplug devices that do not support 64 bit DMA will use bounce
> > buffering.  By changing the flags in device drivers we can force
> > bounce buffering and find missing calls to bus_dmamap_sync().
> > 
> > OK kettenis@ deraadt@
> > 
> > > > On Tue, Jul 28, 2026 at 10:31:10PM -0400, Brad Smith wrote:
> > > > > iwx(4) works with 64-bit DMA.
> > > > > 
> > > > > Tested with
> > > > > 
> > > > > iwx0 at pci0 dev 20 function 3 "Intel Wi-Fi 6 AX201" rev 0x00
> > > > > 
> > > > > 
> > > > 
> > > > Yes, this flag is missing. ok mvs@
> > > > 
> > > > > Index: if_iwx.c
> > > > > ===================================================================
> > > > > RCS file: /cvs/src/sys/dev/pci/if_iwx.c,v
> > > > > retrieving revision 1.229
> > > > > diff -u -p -u -p -r1.229 if_iwx.c
> > > > > --- if_iwx.c	28 May 2026 10:51:52 -0000	1.229
> > > > > +++ if_iwx.c	24 Jul 2026 03:10:09 -0000
> > > > > @@ -12671,6 +12671,7 @@ iwx_attach(struct device *parent, struct
> > > > >  
> > > > >  	ifp->if_softc = sc;
> > > > >  	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
> > > > > +	ifp->if_xflags = IFXF_MBUF_64BIT;
> > > > >  	ifp->if_ioctl = iwx_ioctl;
> > > > >  	ifp->if_start = iwx_start;
> > > > >  	ifp->if_watchdog = iwx_watchdog;
> > > > > 
> > > > 
> >