Re: iwx 64-bit dma

On Wed, Jul 29, 2026 at 07:12:17PM -0600, Theo de Raadt wrote:
> Vitaliy Makkoveev <[email protected]> wrote:
> 
> > On Wed, Jul 29, 2026 at 06:51:49PM -0600, Theo de Raadt wrote:
> > > Vitaliy Makkoveev <[email protected]> wrote:
> > > 
> > > > The IFXF_MBUF_64BIT flag affects only amd64. All other architectures
> > > > still uses memory below 4G. See revision 1.61 of
> > > > sys/arch/amd64/amd64/autoconf.c line 129.
> > > 
> > > I don't see how that matters, that's part of the mechanism for
> > > providing memory to drivers.
> > > 
> > > The diff in question which adds BUS_DMA_64BIT is a declaration to
> > > the higher-level code that _all_ chipsets supported by this driver can
> > > work with 64 bit-addressable memory if the higher levels provide it.
> > > 
> > > If one chipset can't do it, the experience will be terrible.
> > > 
> > > 
> > > 
> > 
> > Well, this means the revision 1.198 of sys/dev/pci/if_iwx.c is wrong and
> > should be reverted.
> 
> No.
> 
> It might answer the question I was asking.

I don't understand your objections. The commit message explicitly says
"this hardware has no issues handling full 64-bit addresses" and the
commit enables 64 bits DMA transfers for *all* iwx(4) chipsets. This
means it can access memory above 4G, right? If so, nothing stops us to
set BUS_DMA_64BIT and allocate mbufs from high memory.

Your suggestion is that some hypothetical iwx(4) chipset does not
support 64 bits DMA transfers. OK, in such case we should follow em(4)
or re(4) way and enable 64 bits DMA transfers *only for* capable
devices:

        if (sc->hw.bus_type == em_bus_type_pci_express)
                sc->sc_dmaflags |= BUS_DMA_64BIT;
	/* ... */
	r = bus_dmamap_create(sc->sc_dmat, ..., sc->sc_dmaflags, ...);
	/* ... */
        if (ISSET(sc->sc_dmaflags, BUS_DMA_64BIT))
                ifp->if_xflags |= IFXF_MBUF_64BIT;


So the current sys/dev/pci/if_iwx.c which enables 64 bits DMA transfers
for all iwx(4) devices, but lefts mbufs allocation from below 4G is
wrong. What is the reason for this BUS_DMA_64BIT flag on iwx(4) if we
don't allow device to access high memory? Why iwx(4) should be special
one? Why don't we follow this way on all devices?