em(4): Panther Lake workarounds

partly from Intel's DPDK driver

tested on 0x57b3 / E1000_DEV_ID_PCH_PTP_I219_LM25 and
0x550b / E1000_DEV_ID_PCH_MTP_I219_V18

diff --git sys/dev/pci/if_em_hw.c sys/dev/pci/if_em_hw.c
index d7e57f344da..ad3fb3d7c22 100644
--- sys/dev/pci/if_em_hw.c
+++ sys/dev/pci/if_em_hw.c
@@ -1204,9 +1204,15 @@ em_reset_hw(struct em_hw *hw)
 			em_pci_set_mwi(hw);
 	}
 	if (IS_ICH8(hw->mac_type)) {
-		uint32_t kab = E1000_READ_REG(hw, KABGTXD);
-		kab |= E1000_KABGTXD_BGSQLBIAS;
-		E1000_WRITE_REG(hw, KABGTXD, kab);
+		uint32_t reg = E1000_READ_REG(hw, KABGTXD);
+		reg |= E1000_KABGTXD_BGSQLBIAS;
+		E1000_WRITE_REG(hw, KABGTXD, reg);
+
+		if (hw->mac_type >= em_pch_ptp) {
+			reg = E1000_READ_REG(hw, CTRL_EXT);
+			reg &= ~E1000_CTRL_EXT_DPG_EN;
+			E1000_WRITE_REG(hw, CTRL_EXT, reg);
+		}
 	}
 
 	if (hw->mac_type == em_82580 || hw->mac_type == em_i350) {
@@ -1559,6 +1565,36 @@ out:
 	return ret_val;
 }
 
+/*
+ * Reconfigure K1 exit timeout as a workaround to the PHY synchronization issue
+ * on MTL, LNL, PTL and WCL.
+ */
+int
+em_reconfigure_k1_exit_timeout(struct em_hw *hw)
+{
+	uint32_t fextnvm12;
+	uint16_t phy_timeout;
+	int r;
+
+	if (hw->mac_type < em_pch_mtp)
+		return E1000_SUCCESS;
+
+	fextnvm12 = E1000_READ_REG(hw, FEXTNVM12);
+	fextnvm12 &= ~E1000_FEXTNVM12_PHYPD_CTRL_MASK;
+	fextnvm12 |= E1000_FEXTNVM12_PHYPD_CTRL_P1;
+	E1000_WRITE_REG(hw, FEXTNVM12, fextnvm12);
+
+	DELAY(1000);
+
+	r = em_read_phy_reg(hw, E1000_PHY_TIMEOUTS_REG, &phy_timeout);
+	if (r)
+		return r;
+	phy_timeout &= ~E1000_PHY_TIMEOUTS_K1_EXIT_TO_MASK;
+	phy_timeout |= 0xF00;
+
+	return em_write_phy_reg(hw, E1000_PHY_TIMEOUTS_REG, phy_timeout);
+}
+
 /******************************************************************************
  * Performs basic configuration of the adapter.
  *
@@ -5899,6 +5935,10 @@ em_phy_reset(struct em_hw *hw)
 		ret_val = em_lv_phy_workarounds_ich8lan(hw);
 		if (ret_val)
 			return ret_val;
+	} else if (hw->mac_type >= em_pch_mtp) {
+		ret_val = em_reconfigure_k1_exit_timeout(hw);
+		if (ret_val)
+			return ret_val;
 	}
 	
 	if (hw->mac_type >= em_pchlan) {
diff --git sys/dev/pci/if_em_hw.h sys/dev/pci/if_em_hw.h
index 82d9e89e47e..b0106379a49 100644
--- sys/dev/pci/if_em_hw.h
+++ sys/dev/pci/if_em_hw.h
@@ -1042,6 +1042,7 @@ struct em_ffvt_entry {
 #define E1000_FEXTNVM3 0x0003C  /* Future Extended NVM 3 - RW */
 #define E1000_FEXTNVM4 0x00024  /* Future Extended NVM 4 - RW */
 #define E1000_FEXTNVM6 0x00010  /* Future Extended NVM 6 - RW */
+#define E1000_FEXTNVM12 0x5BC0  /* Future Extended NVM 12 - RW */
 #define E1000_FCAL     0x00028  /* Flow Control Address Low - RW */
 #define E1000_FCAH     0x0002C  /* Flow Control Address High -RW */
 #define E1000_FCT      0x00030  /* Flow Control Type - RW */
@@ -1320,6 +1321,9 @@ struct em_ffvt_entry {
 #define E1000_FEXTNVM6_REQ_PLL_CLK	0x00000100
 #define E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION	0x00000200
 
+#define E1000_FEXTNVM12_PHYPD_CTRL_MASK	0x00C00000
+#define E1000_FEXTNVM12_PHYPD_CTRL_P1	0x00800000
+
 /* Statistics counters collected by the MAC */
 struct em_hw_stats {
     uint64_t crcerrs;
@@ -1527,6 +1531,7 @@ struct em_hw {
 #define E1000_CTRL_FORCE_PHY_RESET 0x00008000 /* Reset both PHY ports, through PHYRST_N pin */
 #define E1000_CTRL_LANPHYPC_OVERRIDE 0x00010000 /* SW control of LANPHYPC */
 #define E1000_CTRL_LANPHYPC_VALUE    0x00020000 /* SW value of LANPHYPC */
+#define E1000_CTRL_EXT_DPG_EN        0x00000008 /* Dynamic Power Gating Enable */
 #define E1000_CTRL_EXT_FORCE_SMBUS   0x00000800 /* Force SMBus mode */
 #define E1000_CTRL_EXT_PHYPDEN       0x00100000
 #define E1000_I2CCMD_REG_ADDR_SHIFT	16
@@ -3784,6 +3789,10 @@ union ich8_hws_flash_regacc {
 #define I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK	0x3F00
 #define I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT	8
 
+/* PHY Timeouts */
+#define E1000_PHY_TIMEOUTS_REG				PHY_REG(770, 21)
+#define E1000_PHY_TIMEOUTS_K1_EXIT_TO_MASK		0x0FC0
+
 /* PHY Low Power Idle Control */
 #define I82579_LPI_CTRL				PHY_REG(772, 20)
 #define I82579_LPI_CTRL_ENABLE_MASK		0x6000