Re: Plan 9 C compiler for Xtensa CPUs
Cyber Fonic <[email protected]>
| Newsgroups | gmane.os.plan9.general |
|---|---|
| Message-ID | <CALj3Nd3gDva4G=cWgivx5HNccgFYfErusmPSVO0Rbz59xmHb_w@mail.gmail.com> |
Does anybody have any suggestions as to what it would take to create a C compiler for Xtensa (it is basically a 32 bit sorta-like RISC architecture)? Since C compilers do exist for Xtensa (both Arduino and ESIF) , is it at all possible to port Plan 9 C compilers using a "host" compiler as a semi-bootstrap? Or would it be more effectively to use an existing Plan 9 system, grab the sources for a similar compiler, e.g. MIPS and start building a Xtensa / ESP-32 specific one? On Fri, 26 Jul 2019 at 20:31, Charles Forsyth <[email protected]> wrote: > I was thinking of doing that since I've got an ESP-32 for some reason > > On Fri, Jul 26, 2019 at 7:38 AM Cyber Fonic <[email protected]> wrote: > >> I was reading the post Why Didn't Plan 9 Succeed >> <https://news.ycombinator.com/item?id=20527650> on Hacker News. >> >> Made me think that Plan 9 for IoT system of systems could be viable. >> >> To that end, ESP-32 modules look capable enough to run Plan 9, but is >> there a Plan 9 C compiler for Xtensa ISA CPUs? >> >>