Re: Plan 9 C compiler for Xtensa CPUs
Lucio De Re <[email protected]>
| Newsgroups | gmane.os.plan9.general |
|---|---|
| Message-ID | <CAJQ9t7iyXQm=OKUT6HKDidPpFQ4A5F78KfJ0026cWCkHDrod4A@mail.gmail.com> |
On 8/7/19, Charles Forsyth <[email protected]> wrote: > I've not previously seen an architecture where so many cache and TLB > control instructions were in the primary space and took up so much of it. > I guess the remainder is RISC :-). Lucio.