Re: FSM vs. Petri nets for component modelling...

On Fri, 7 Dec 2001, Daniel Simon wrote:

Thanks (again!) for the insightful answers! I'm really enjoying this
discussion.

> >What are the system calls in your current implementation?
> All tasks (control, FSM, clocks) are under control of the RTOS (VxWorks and
> soon RTAI, also solaris and linux for soft rt).

This is exactly the topic of the discussions in our group at this
moment: how to find an appropriate sequencing tool for real-time, and
how to implement it in a way which is as RTOS-independent as possible.
I'm _very_ interested in sharing ideas on this topic.

> Thus system calls are e.g.  pthread_create(), SemGive() to unlock a
> control task, msqQSend to send a event and awake the automaton...

How much effort do you want to spend on making these calls POSIX
compatible? (I, for one, would be willing to go _very_ far in this respect.)

> >Esterel...Can you explain in what sense it can harm?
> OK, not harm, but difficult. It requires experience to avoid some subtle
> traps, e.g. instantaneous loops and circuits (something well understood by
> people coming from digital hardware). Also, even if the compiler checks for
> many things, it cannot detect your specification errors, even if formal
> verification can also help at this level.

Okay, I see what you mean. Personally, I don't think this is a
problem, because an ``advanced user'' is an advanced user anyway,
i.e., aware of the pitfalls of the tools and applications.

> >about Esterel and Signal: my personal experience is that problems which are
> easyly stated with Esterel are very difficult to handle in Signal and
> conversely.

Mmmm, does this reflect a fundamentally different design, or just
inappropriate syntax?

Herman