[ playerstage-Patches-3296942 ] diocmd clk signal generation ability

Patches item #3296942, was opened at 2011-05-03 16:07
Message generated for change (Tracker Item Submitted) made by newchief
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Category: Player
Group: Release-3.0
Status: Open
Resolution: None
Priority: 5
Private: No
Submitted By: Paul Osmialowski (newchief)
Assigned to: Rich Mattes (jpgr87)
Summary: diocmd clk signal generation ability

Initial Comment:
This patch adds two new options to diocmd which causes it can emit clock signal of any given duty cycle.

Example:
driver                                                                                                                                                                                  
(                                                                                                                                                                                       
  name "diocmd"                                                                                                                                                                         
  provides ["dio:0"]                                                                                                                                                                    
  wait_on_normal 0.7                                                                                                                                                                    
  wait_on_opposite 0.3                                                                                                                                                                  
  bits "010"                                                                                                                                                                            
  alwayson 1                                                                                                                                                                            
  read_only 0                                                                                                                                                                           
)

Three lowest bits emitted by this dio device are three clock signals with 30%, 70% and 30% duty cycle (the "normal" state is the state at time 0, which here is 0 for first and last clock and 1 for the middle clock; normal state lasts for 0.7sec. while opposite state lasts for 0.3sec.; these settings can be chanded at run time by diogui gtk+ application).


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