[PATCH] VHDL Component Instantiation Fixes
Robert Abel <[email protected]> Sat, 17 Mar 2012 07:39:21 +0100
| Newsgroups | gmane.text.doxygen.devel |
|---|---|
| Message-ID | <[email protected]> |
Hi, I noticed that component instantiations were handled improperly: Doubly instantiated components were just hidden and not documented at all. This resulted in wrong documentation. The original hack (keeping a list inside the parser) might have been intended to relieve the "inheritance graphs" of some clutter, but that did not work properly either. Component Instances would also point to "dummy.html" instead of their containing architecture's page. I fixed that quick and dirty as well. Still, the whole VHDL module seems like one big hack anyway :-/ Patch is against the latest trunk. Signed-off-by: Robert Abel <[email protected]> ------------------------------------------------------------------------------ This SF email is sponsosred by: Try Windows Azure free for 90 days Click Here http://p.sf.net/sfu/sfd2d-msazure _______________________________________________ Doxygen-develop mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/doxygen-develop
0001-fix-VHDL.patch
(text/plain, 5.8 KB)
diff -Naur doxygena/src/classdef.cpp doxygen/src/classdef.cpp
--- doxygena/src/classdef.cpp 2012-03-17 07:28:12.739596100 +0100
+++ doxygen/src/classdef.cpp 2012-03-17 05:59:25.844915100 +0100
@@ -2529,7 +2529,7 @@
// returns TRUE iff class definition `bcd' represents an (in)direct base
// class of class definition `cd'.
-bool ClassDef::isBaseClass(ClassDef *bcd, bool followInstances,int level)
+bool ClassDef::isBaseClass(ClassDef *bcd, bool followInstances,int level, int maxlevel)
{
bool found=FALSE;
//printf("isBaseClass(cd=%s) looking for %s\n",name().data(),bcd->name().data());
@@ -2551,8 +2551,46 @@
//printf("isBaseClass() baseclass %s\n",ccd->name().data());
if (ccd==bcd)
found=TRUE;
- else
- found=ccd->isBaseClass(bcd,followInstances,level+1);
+ else {
+ if (level < maxlevel)
+ found=ccd->isBaseClass(bcd,followInstances,level+1);
+ }
+ }
+ }
+ return found;
+}
+
+//----------------------------------------------------------------------
+// recursive function:
+// returns TRUE iff class definition `scd' represents an (in)direct sub
+// class of class definition `cd'.
+
+bool ClassDef::isSubClass(ClassDef *scd, bool followInstances,int level, int maxlevel)
+{
+ bool found=FALSE;
+ //printf("isBaseClass(cd=%s) looking for %s\n",name().data(),bcd->name().data());
+ if (level>256)
+ {
+ err("Possible recursive class relation while inside %s and looking for %s\n",qPrint(name()),qPrint(scd->name()));
+ abort();
+ return FALSE;
+ }
+ if (subClasses())
+ {
+ // Beware: trying to optimise the iterator away using ->first() & ->next()
+ // causes bug 625531
+ BaseClassListIterator bcli(*subClasses());
+ for ( ; bcli.current() && !found ; ++bcli)
+ {
+ ClassDef *ccd=bcli.current()->classDef;
+ if (!followInstances && ccd->templateMaster()) ccd=ccd->templateMaster();
+ //printf("isSubClass() subclass %s\n",ccd->name().data());
+ if (ccd==scd)
+ found=TRUE;
+ else {
+ if (level < maxlevel)
+ found=ccd->isBaseClass(scd,followInstances,level+1);
+ }
}
}
return found;
diff -Naur doxygena/src/classdef.h doxygen/src/classdef.h
--- doxygena/src/classdef.h 2012-03-17 07:28:12.562586000 +0100
+++ doxygen/src/classdef.h 2012-03-17 05:54:27.936875800 +0100
@@ -184,7 +184,9 @@
* class. This function will recusively traverse all branches of the
* inheritance tree.
*/
- bool isBaseClass(ClassDef *bcd,bool followInstances,int level=0);
+ bool isBaseClass(ClassDef *bcd,bool followInstances,int level=0, int maxlevel=257);
+
+ bool isSubClass(ClassDef *scd, bool followInstances,int level=0, int maxlevel=257);
/*! returns TRUE iff \a md is a member of this class or of the
* the public/protected members of a base class
diff -Naur doxygena/src/vhdldocgen.cpp doxygen/src/vhdldocgen.cpp
--- doxygena/src/vhdldocgen.cpp 2012-03-17 07:28:09.341000000 +0100
+++ doxygen/src/vhdldocgen.cpp 2012-03-17 07:22:41.019622800 +0100
@@ -1565,7 +1565,7 @@
// start a new member declaration
bool isAnonymous = annoClassDef; // || m_impl->annMemb || m_impl->annEnumType;
- ///printf("startMemberItem for %s\n",name().data());
+ //printf("startMemberItem for %s\n",mdef->name().data());
ol.startMemberItem( mdef->anchor(), isAnonymous ); //? 1 : m_impl->tArgList ? 3 : 0);
// If there is no detailed description we need to write the anchor here.
@@ -1688,6 +1688,7 @@
case VhdlDocGen::COMPONENT:
case VhdlDocGen::INSTANTIATION:
case VhdlDocGen::CONFIG:
+
if (VhdlDocGen::isCompInst(mdef) )
{
nn=largs;
@@ -1866,6 +1867,7 @@
bool first=TRUE;
MemberDef *md;
MemberListIterator mli(*mlist);
+
for ( ; (md=mli.current()); ++mli )
{
int mems=md->getMemberSpecifiers();
@@ -2687,7 +2689,12 @@
QCString bName=classEntity->name();
//bName+="::"+cur->name;
- cd->insertBaseClass(classEntity,bName,Public,Normal,0);
+ //printf("addInstance %s to %s\n", cd->name().data(), classEntity->name().data());
+
+ if (!cd->isBaseClass(classEntity, true, 0, 0)) {
+ //printf("!isBaseClass\n");
+ cd->insertBaseClass(classEntity,bName,Public,Normal,0);
+ }
QCString n1=cur->name+"::"+cur->type;
// n1+="::"+cur->name;
@@ -2697,7 +2704,12 @@
// if (archBind)
// cd->insertSubClass(archBind,Public,Normal,0);
// else
- classEntity->insertSubClass(cd,Public,Normal,0);
+
+ if (!classEntity->isSubClass(cd, true, 0, 0)) {
+ //printf("!isSubClass\n");
+ classEntity->insertSubClass(cd,Public,Normal,0);
+
+ }
if (ar==0) return;
QCString uu=cur->name;
@@ -2708,13 +2720,27 @@
MemberDef::Variable,
0,
0);
+
+ if (ar->getOutputFileBase()) {
+
+ TagInfo tg;
+ tg.anchor = 0;
+ tg.fileName = ar->getOutputFileBase();
+ tg.tagName = 0;
+
+ md->setTagInfo(&tg);
+
+ }
+
md->setLanguage(SrcLangExt_VHDL);
md->setMemberSpecifiers(VhdlDocGen::INSTANTIATION);
md->setBriefDescription(cur->brief,cur->briefFile,cur->briefLine);
md->setBodySegment(cur->startLine,-1) ;
FileDef *fd=ar->getFileDef();
md->setBodyDef(fd);
+
ar->insertMember(md);
+
// printf("\nMemberreference [%p]",md);
}
diff -Naur doxygena/src/vhdlparser.y doxygen/src/vhdlparser.y
--- doxygena/src/vhdlparser.y 2012-03-17 07:28:09.093000000 +0100
+++ doxygen/src/vhdlparser.y 2012-03-17 04:09:12.183635300 +0100
@@ -2115,12 +2115,11 @@
if (lastCompound)
{
current->args=lastCompound->name;
- if (!findInstant(current->type))
- {
- initEntry(current);
- instFiles.append(new Entry(*current));
- }
+
+ initEntry(current);
+ instFiles.append(new Entry(*current));
current->reset();
+
}
else
{