Bug(?) VHDL UML class diagrams contain libraries and use clauses as members

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Hi everyone,
I am using doxygen to document my VHDL code, and I activated the "UML_LOOK
= YES" option, to generate UML style diagrams.
I noticed, that the Libraries (like "ieee") and Use Clauses (like
std_logic_1164) are listed as public members in the diagrams (see attached
image, or github project, below). In my opinion they should be treated like
"#include" statements in C.

I have provided an example project here:
https://github.com/StefanD986/doxygen_vhdl_bug_example

You don't need any vhdl compiler to test it. Just clone and build the
doxygen documentation in doc/.

-- Stefan

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<div dir=3D"ltr">Hi everyone,<div>I am using doxygen to document my VHDL co=
de, and I activated the &quot;UML_LOOK =3D YES&quot; option, to generate UM=
L style diagrams.</div><div>I noticed, that the Libraries (like &quot;ieee&=
quot;) and Use Clauses (like std_logic_1164) are listed as public members i=
n the diagrams (see attached image, or github project, below). In my opinio=
n they should be treated like &quot;#include&quot; statements in C.</div><d=
iv><br></div><div>I have provided an example project here:=C2=A0<a href=3D"=
https://github.com/StefanD986/doxygen_vhdl_bug_example">https://github.com/=
StefanD986/doxygen_vhdl_bug_example</a></div><div><br></div><div>You don&#3=
9;t need any vhdl compiler to test it. Just clone and build the doxygen doc=
umentation in doc/.</div><div><br></div><div>-- Stefan</div></div>

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