Verilog support in Doxygen

Hi!

 

A number of people have expressed interest in supporting Verilog in Doxygen.
We would like to kick start this initiative and we wanted to find out if
there is anyone else interested in participating. We are currently a group
of three.

 

Any comments or insights are greatly appreciated especially from developers
who are trying to support languages like Matlab, Perl, VB, Python .etc. 

 

Cheers,

Mohammad