Re: VHDL Hierachy

True, now that you mention it I remember that I also had two entities
that didn't show up in the graph at first, because I also used
direct-instantiation for the two missing entities. I usually never do
that, only for these two missing entities I was too lazy. (What I
usually do is I add the component declarations to a package, which I
include at the top of my file. That gives a better overview what is
used in the entity, but also keeps the architecture declarative part
clean.)

I just added the component declarations of my two missing entities to
the package that I include, and changed the instantiation and that
solved it for me. But if "a_module" is auto-generated I guess thats
not an option for you.

On the other hand: If a_module is auto-generated, you cannot add
doxygen comments to it. And since its generated, the inner structure
of a_module shouldn't be of concern anyway, in my opinion. Instead
maybe the settings/options of the generating script/program should be
documented.

But yeah, I know what you mean. I try to avoid generated code as much
as possible. But there is not always a way around it.

And it definitely is a bug in the doxygen parser. (Sadly Doxygen for
VHDL is not very good anyway (e.g. the UML class diagrams are almost
useless). Unfortunately there are no real alternative I guess.

2016-06-03 18:51 GMT+02:00  <[email protected]>:
> Hey Stefan,
>
>
>
> I have uploaded some sample code to
> http://github.com/martynp/doxygen_vhdl_test/. I tried your settings file and
> it did not work still…
>
>
>
> With doxygen 1.8.5 (CentOS 7 default version):
>
>
>
> https://github.com/martynp/doxygen_vhdl_test/blob/master/1.8.5.png
>
>
>
> With doxygen 1.8.12:
>
>
>
> https://github.com/martynp/doxygen_vhdl_test/blob/master/1.8.12.png
>
>
>
> I had a play with most of the settings I could find – but doxygen is not
> figuring out the entity relationships. It works if I use components, but I
> would rather not (there are auto-generated parts of the code which will not
> work without major changes).
>
>
>
> Thanks!
>
>
>
> -          Martyn
>
>
>
> From: [email protected] [mailto:[email protected]] On Behalf Of Stefan
> Dröge
> Sent: 03 June 2016 10:17
> To: Martyn Pittuck <[email protected]>
> Cc: [email protected]
> Subject: Re: [Doxygen-users] VHDL Hierachy
>
>
>
> With hierarchy you mean something like that the diagram below? That was
> generated for my VHDL code with doxygen Version 1.8.11 and the attached
> Doxyfile.
>
>
>
> (In case attachements do not work on the mailinglist here is a link:
> https://www.dropbox.com/s/pdpybkpstxx73uq/Screenshot%202016-06-03%2011.08.24.png?dl=0
> )
>
>
>
> 2016-06-03 9:55 GMT+02:00 Martyn Pittuck <[email protected]>:
>
> Hello,
>
>  - Martyn
>
>
>
>
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