Re: IBM - New SUB-Nanometer STACKED Chip

c186282 <[email protected]> Mon, 29 Jun 2026 01:39:39 -0400

Newsgroups	comp.os.linux.misc,alt.comp.hardware.pc-homebuilt,alt.magic.secrets,alt.conspiracy
Organization	wokiesux
Message-ID	<[email protected]>

On 6/29/26 01:11, Mr. Man-wai Chang wrote:
> On 6/29/2026 2:09 AM, Charlie Gibbs wrote:
>> On 2026-06-28, c186282 <[email protected]> wrote:
>>>
>>> IBM unveils sub-1-nanometer chip architecture that stacks 100
>>> billion transistors onto a fingernail-sized processor
>>>
>>> . . .
>>>
>>>     Pretty impressive ... and stacking two (three?) layers
>>>     really packs a lot in.
>>>
>>>     NOT sure how they deal with the HEAT in the stacked
>>>     design.
>>>
>>>     100 billion ... how many in the i4004 ?
>>
>> Dunno - but I do remember that manufacturers hit a wall for
>> a while when trying to get below 1 micrometer.  It took some
>> time before memory chips larger than 64K became available.
> 
> Wall? Or Seal? :)

   Amazed they were able to get this small - but do
   expect a wall/seal is pretty much here. We're
   talking kinda atomic dimensions now - nowhere else
   to go using any conventional approaches. Anything
   much further won't be 'electronics' as we know it,
   some kind of weird quantum stuff.

   STABLE deca-state logic maybe ?