Re: [PATCH] Revert "x86/fpu: Refine and simplify the magic number check during signal return"

On Fri, May 1, 2026 at 12:13=E2=80=AFPM Chang S. Bae <chang.seok.bae@intel.=
com> wrote:
>
> On 5/1/2026 11:44 AM, Andrei Vagin wrote:
> >
> > I've been thinking about this more, and I believe the claim that XSAVE
> > offsets can differ across CPUs for the same feature is inaccurate. The
> > XSAVE standard format uses fixed offsets specifically to allow migratio=
n
> > between different CPU generations. If a feature exists on both the
> > source and destination CPUs, its data resides at the exact same byte
> > offset.
>
> There is commit ba386777a30b ("x86/elf: Add a new FPU buffer layout info
> to x86 core files") for this reason:
>
>      ...
>      The XSAVE layouts of modern AMD and Intel CPUs differ, especially
>      since Memory Protection Keys and the AVX-512 features have been
>      inculcated into the AMD CPUs.
>
>      Since AMD never adopted (and hence never left room in the XSAVE
>      layout for) the Intel MPX feature, tools like GDB had assumed a
>      fixed XSAVE layout matching that of Intel (based on the XCR0 mask).
>
>      Hence, core dumps from AMD CPUs didn't match the known size for the
>      XCR0 mask. This resulted in GDB and other tools not being able to
>      access the values of the AVX-512 and PKRU registers on AMD CPUs.
>      ...

This is a different; here, we have two different CPU vendors where XSAVE
layouts differ. The XSAVE layout itself is not the only reason why migratio=
n
between Intel and AMD cannot work reliably.

Thanks,
Andrei