[PATCH 2/3] PCI: imx6: Use the external clock as REF_CLK when needed for i.MX8MQ

Rudi Heitbaum <[email protected]> Sun, 2 Aug 2026 11:32:00 +0000
Newsgroups dev.linux.lists.imx,org.infradead.lists.linux-arm-kernel,org.kernel.vger.linux-devicetree,org.kernel.vger.linux-kernel,org.kernel.vger.linux-pci
Message-ID <563f057f26b1147a79392509b35dcb7f18113ba9.1785669457.git.rudi@heitbaum.com>
i.MX8MQ has two PCIe REF_CLK sources: an off-chip oscillator and the
internal PLL. The driver unconditionally selected the oscillator, which
is what the

	/* TODO: This code assumes external oscillator is being used */

comment refers to. Boards wiring an oscillator to the pad describe it as
the "pcie_bus" clock, but nothing in the driver looks that clock up by
name, so it does not select anything.

Reuse the generic enable_ext_refclk flag, set when an "extref" clock is
supplied, to select between the two, as is already done for i.MX95 in
commit d8574ce57d76 ("PCI: imx6: Add external reference clock input mode
support").

Signed-off-by: Rudi Heitbaum <[email protected]>
---
 drivers/pci/controller/dwc/pci-imx6.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index dcdeba1856f7..5a350b458782 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -445,11 +445,16 @@ static int pcie_phy_write(struct imx_pcie *imx_pcie, int addr, u16 data)
 
 static int imx8mq_pcie_init_phy(struct imx_pcie *imx_pcie)
 {
-	/* TODO: This code assumes external oscillator is being used */
+	bool ext = imx_pcie->enable_ext_refclk;
+
+	/*
+	 * Select the off-chip oscillator as REF_CLK when an "extref" clock is
+	 * supplied, otherwise fall back to the internal PLL.
+	 */
 	regmap_update_bits(imx_pcie->iomuxc_gpr,
 			   imx_pcie_grp_offset(imx_pcie),
 			   IMX8MQ_GPR_PCIE_REF_USE_PAD,
-			   IMX8MQ_GPR_PCIE_REF_USE_PAD);
+			   ext ? IMX8MQ_GPR_PCIE_REF_USE_PAD : 0);
 	/*
 	 * Per the datasheet, the PCIE_VPH is suggested to be 1.8V.  If the
 	 * PCIE_VPH is supplied by 3.3V, the VREG_BYPASS should be cleared
-- 
2.53.0