Re: [PATCH 1/3] dt-bindings: pci: fsl,imx6q-pcie: Add extref clock for i.MX8MQ

Thank you for your contribution! Sashiko AI review found 1 potential issue(=
s) to consider:
- [Medium] The optional 'extref' clock was added to the Root Complex bindin=
g for i.MX8MQ but omitted from the corresponding Endpoint mode binding, res=
ulting in schema validation failure if the endpoint uses the clock.
--

--- Patch [1]: [PATCH 1/3] dt-bindings: pci: fsl,imx6q-pcie: Add extref clo=
ck for i.MX8MQ ---
commit 4169458ec9055f45e1c7d18a9eea850e75cf9b6a
Author: Rudi Heitbaum <[email protected]>

dt-bindings: pci: fsl,imx6q-pcie: Add extref clock for i.MX8MQ

i.MX8MQ can drive PCIe REF_CLK either from the internal PLL or from an
off-chip oscillator. This allows an optional fifth extref clock to describe
the latter, matching the name already used for i.MX95.

> diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/=
Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> index e8b8131f5f23b..8fb0c919ae572 100644
> --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml

[ ... ]

> @@ -173,13 +174,16 @@ allOf:
>      then:
>        properties:
>          clocks:
> -          maxItems: 4
> +          minItems: 4
> +          maxItems: 5
>          clock-names:
> +          minItems: 4
>            items:
>              - const: pcie
>              - const: pcie_bus
>              - const: pcie_phy
>              - const: pcie_aux
> +            - const: extref  # Optional

[Severity: Medium]
Will this same clock be used when the hardware is configured in endpoint mo=
de?

Currently, this adds the optional extref clock to the root complex binding =
for
fsl,imx8mq-pcie, expanding the maximum items to 5. However, the correspondi=
ng
endpoint schema in fsl,imx6q-pcie-ep.yaml for fsl,imx8mq-pcie-ep still
restricts clocks to exactly 4 items:

Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml:
  - if:
      properties:
        compatible:
          enum:
            - fsl,imx8mq-pcie-ep
            - fsl,imx95-pcie-ep
    then:
      properties:
        clocks:
          minItems: 4
          maxItems: 4

If an endpoint device tree describes the hardware using this 5th extref clo=
ck,
will it fail schema validation because the endpoint binding was not also
updated?

--=20
Sashiko AI review =C2=B7 https://sashiko.dev/#/patchset/cover.1785669457.gi=
[email protected]?part=3D1