RE: [PATCH v4] PCI: imx6: Update MPLLB bandwidth to improve i.MX95 Gen3 PCIe stability

> -----Original Message-----
> From: Bjorn Helgaas <[email protected]>
> Sent: Saturday, August 1, 2026 12:03 AM
> To: Hongxing Zhu (OSS) <[email protected]>
> Cc: Frank Li <[email protected]>; [email protected]; lpieralisi@kerne=
l.org;
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; linux-arm-
> [email protected]; [email protected]; [email protected]=
.org;
> Hongxing Zhu <[email protected]>
> Subject: Re: [PATCH v4] PCI: imx6: Update MPLLB bandwidth to improve i.MX=
95
> Gen3 PCIe stability
>=20
> On Fri, Jul 31, 2026 at 11:05:46AM +0800, [email protected] wrote:
> > From: Richard Zhu <[email protected]>
> >
> > Bandwidth marginality was observed during i.MX95 Gen3 PCIe tests with
> > the default MPLLB_BANDWIDTH value (120). This margin degradation
> > worsens across voltage and temperature (VT) variations and different
> > test matrices, potentially causing link stability issues.
> >
> > Testing with MPLLB_BANDWIDTH value of 140 (0x8c) shows significant
> > improvement in bandwidth margins across all VT conditions and test
> > scenarios.
> >
> > Implement PHY register write helper function and configure:
> > - MPLLB_BW_OVRD_IN =3D 140 (0x8c) for improved bandwidth margin
> > - MPLLB_BW_OVRD_EN to enable the override
> >
> > This ensures robust PCIe Gen3 performance across all operating
> > conditions.
>=20
> Thanks for including the previous and new MPLLB_BANDWIDTH values.
>=20
> I'm fine with the patch, but I think "bandwidth marginality" is awkward w=
ording
> because "marginality" doesn't seem to be commonly used in this context.  =
Maybe
> something like:
>=20
>   We observed poor bandwidth margins during ...  The margins worsened
>   across ...
Understood. I'm totally fine with these updates.
Thanks for your kind review.

Best Regards
Richard Zhu