RE: [REGRESSION] mainline/master: Apalis iMX6 no longer boots

NXP Confidential
> -----Original Message-----
> From: Francesco Dolcini <[email protected]>
> Sent: Tuesday, August 11, 2026 2:38 PM
> To: Hongxing Zhu (OSS) <[email protected]>
> Cc: Leonardo Costa <[email protected]>; Bjorn Helgaas
> <[email protected]>; [email protected]; [email protected];
> [email protected]; Frank Li <[email protected]>; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; linux-arm-
> [email protected]; [email protected];
> [email protected]; Sherry Sun <[email protected]>; Manivannan
> Sadhasivam <[email protected]>; Hongxing Zhu <[email protected]>;
> [email protected]
> Subject: Re: [REGRESSION] mainline/master: Apalis iMX6 no longer boots
>
> On Tue, Aug 11, 2026 at 12:47:18AM +0000, Hongxing Zhu (OSS) wrote:
> > > -----Original Message-----
> > > From: Leonardo Costa <[email protected]>
> > > Sent: Tuesday, August 11, 2026 2:26 AM
> > > To: Hongxing Zhu (OSS) <[email protected]>
> > > Cc: Bjorn Helgaas <[email protected]>; [email protected];
> > > [email protected]; [email protected]; Frank Li
> > > krzk+<[email protected]>;
> > > [email protected]; [email protected]; [email protected];
> > > [email protected]; [email protected];
> > > [email protected]; [email protected]; linux-
> > > [email protected]; [email protected]; Sherry Sun
> > > <[email protected]>; Manivannan Sadhasivam <[email protected]>;
> > > Hongxing Zhu <[email protected]>; [email protected]
> > > Subject: Re: [REGRESSION] mainline/master: Apalis iMX6 no longer
> > > boots
> > >
> > > On Thu, Jul 16, 2026 at 02:09:19PM -0300, Leonardo Costa wrote:
> > > > On Thu, Jul 16, 2026 at 02:15:42AM +0000, Hongxing Zhu (OSS) wrote:
> > > > > Hi Leonardo,
> > > > >
> > > > > Would you be able to test this patch on your affected boards?
> > > > > Your testing would help expedite the merge process and ensure
> > > > > the fix resolves the boot issue you're experiencing.
> > > > >
> > > > > Best Regards
> > > > > Richard Zhu
> > > >
> > > > Hi Richard,
> > > >
> > > > Sorry for taking long to respond, I was caught up with something.
> > > > I tested the patch and it solved the issue. I sent a Tested-by tag there.
> > > > Thanks for looking into this!
> > > >
> > > > Best Regards
> > > > Leonardo
> > >
> > > Hi Richard,
> > >
> > > That patch might have introduced/exposed a second regression where
> > > PCI devices are not linked properly during the initialization. Sorry
> > > for not catching this before, as I didn't have any device connected during
> the previous test.
> > Hi Leonardo:
> > Sorry to hear about that.
> > I did test commit 7678e81498e2 with one Intel NIC (82574L) connected,
> > and I've double-checked today based on v7.2-rc7. The PCIe link can be
> > set up properly on the i.MX6Q Sabresd board in my testing.
> >
> > Here are the logs:
> > root@imx6qpdlsolox:~# lspci
> > 00:00.0 PCI bridge: Synopsys, Inc. DWC_usb3 / PCIe bridge (rev 01)
> > 01:00.0 Ethernet controller: Intel Corporation 82574L Gigabit Network
> > Connection root@imx6qpdlsolox:~# uname -a Linux imx6qpdlsolox
> > 7.2.0-rc7 #30 SMP Tue Aug 11 00:21:26 UTC 2026 armv7l GNU/Linux
> > root@imx6qpdlsolox:~# dmesg | grep pci
> > [    0.256138] imx6q-pcie 1ffc000.pcie: host bridge /soc/pcie@1ffc000 ranges:
> > [    0.256307] imx6q-pcie 1ffc000.pcie:       IO 0x0001f80000..0x0001f8ffff ->
> 0x0000000000
> > [    0.256339] imx6q-pcie 1ffc000.pcie:      MEM 0x0001000000..0x0001efffff -
> > 0x0001000000
> > [    0.256434] imx6q-pcie 1ffc000.pcie: config reg[1] 0x01f00000 == cpu
> 0x01f00000
> > [    0.458388] imx6q-pcie 1ffc000.pcie: iATU: unroll F, 4 ob, 4 ib, align 64K,
> limit 4G
> > [    0.458492] imx6q-pcie 1ffc000.pcie: Link: Only Gen1 is enabled
> > [    0.555294] imx6q-pcie 1ffc000.pcie: PCIe Gen.1 x1 link up
> > [    0.555783] imx6q-pcie 1ffc000.pcie: PCI host bridge to bus 0000:00
> > ...
> >
> > The following endpoint devices also yielded the same results.
> > root@imx6qpdlsolox:~# lspci
> > 00:00.0 PCI bridge: Synopsys, Inc. DWC_usb3 / PCIe bridge (rev 01)
> > 01:00.0 Network controller: Qualcomm Atheros AR9287 Wireless Network
> > Adapter (PCI-Express) (rev 01) root@imx6qpdlsolox:~# uname -a Linux
> > imx6qpdlsolox 7.2.0-rc7 #30 SMP Tue Aug 11 00:21:26 UTC 2026 armv7l
> > GNU/Linux ...
> >
> > root@imx6qpdlsolox:~# lspci
> > 00:00.0 PCI bridge: Synopsys, Inc. DWC_usb3 / PCIe bridge (rev 01)
> > 01:00.0 USB controller: NEC Corporation uPD720200 USB 3.0 Host
> > Controller (rev 04) root@imx6qpdlsolox:~# uname -a Linux imx6qpdlsolox
> > 7.2.0-rc7 #30 SMP Tue Aug 11 00:21:26 UTC 2026 armv7l GNU/Linux
> >
> > Could you provide more details of your hardware setup (board,
> > connected devices, PERST# present or not)?
> > This may help us identify if there's a specific scenario that triggers
> > the regression you're experiencing.
>
> It's an apalis imx6, as reported already in this email thread.
> The DT is in Linux, you can check
> arch/arm/boot/dts/nxp/imx/imx6q-apalis-ixora-v1.2.dts every details about
> PERST# and more.
>
> This is the device connected:
>
> 00:00.0 PCI bridge: Synopsys, Inc. DWC_usb3 / PCIe bridge (rev 01)
> 01:00.0 SATA controller: ASMedia Technology Inc. ASM1061/ASM1062 Serial
> ATA Controller (rev 02)
>
> 01:00.0 SATA controller: ASMedia Technology Inc. ASM1061/ASM1062 Serial
> ATA Controller (rev 02) (prog-if 01 [AHCI 1.0])
>       Subsystem: ASMedia Technology Inc. ASM1061/ASM1062 Serial ATA
> Controller
>       Flags: bus master, fast devsel, latency 0, IRQ 308
>       I/O ports at 1020 [size=8]
>       I/O ports at 1030 [size=4]
>       I/O ports at 1028 [size=8]
>       I/O ports at 1034 [size=4]
>       I/O ports at 1000 [size=32]
>       Memory at 01100000 (32-bit, non-prefetchable) [size=512]
>       Expansion ROM at 01200000 [virtual] [disabled] [size=64K]
>       Capabilities: [50] MSI: Enable+ Count=1/1 Maskable- 64bit-
>       Capabilities: [78] Power Management version 3
>       Capabilities: [80] Express Legacy Endpoint, IntMsgNum 0
>       Capabilities: [100] Virtual Channel
>       Kernel driver in use: ahci
>       Kernel modules: ahci
>
>
> These are some working logs from a 6.6.151 kernel
>
> [    0.233058] imx6q-pcie 1ffc000.pcie: host bridge /soc/pcie@1ffc000 ranges:
> [    0.233112] imx6q-pcie 1ffc000.pcie:       IO 0x0001f80000..0x0001f8ffff ->
> 0x0000000000
> [    0.233144] imx6q-pcie 1ffc000.pcie:      MEM 0x0001000000..0x0001efffff ->
> 0x0001000000
> [    0.465779] imx6q-pcie 1ffc000.pcie: iATU: unroll F, 4 ob, 4 ib, align 64K, limit
> 4G
> [    0.564230] imx6q-pcie 1ffc000.pcie: PCIe Gen.1 x1 link up
> [    0.564249] imx6q-pcie 1ffc000.pcie: Link: Only Gen1 is enabled
> [    0.564259] imx6q-pcie 1ffc000.pcie: Link up, Gen1
> [    0.564272] imx6q-pcie 1ffc000.pcie: PCIe Gen.1 x1 link up
> [    0.564778] imx6q-pcie 1ffc000.pcie: PCI host bridge to bus 0000:00
> [    0.564795] pci_bus 0000:00: root bus resource [bus 00-ff]
> [    0.564809] pci_bus 0000:00: root bus resource [io  0x0000-0xffff]
> [    0.564821] pci_bus 0000:00: root bus resource [mem 0x01000000-0x01efffff]
> [    0.564864] pci 0000:00:00.0: [16c3:abcd] type 01 class 0x060400
> [    0.564886] pci 0000:00:00.0: BAR 0 [mem 0x00000000-0x000fffff]
> [    0.564905] pci 0000:00:00.0: ROM [mem 0x00000000-0x0000ffff pref]
> [    0.564917] pci 0000:00:00.0: PCI bridge to [bus 01-ff]
> [    0.564931] pci 0000:00:00.0:   bridge window [io  0x0000-0x0fff]
> [    0.564943] pci 0000:00:00.0:   bridge window [mem 0x00000000-0x000fffff]
> [    0.564957] pci 0000:00:00.0:   bridge window [mem 0x00000000-0x000fffff
> pref]
> [    0.565405] pci 0000:00:00.0: Limiting cfg_size to 512
> [    0.565455] pci 0000:00:00.0: supports D1
> [    0.565465] pci 0000:00:00.0: PME# supported from D0 D1 D3hot D3cold
> [    0.574310] pci 0000:01:00.0: [1b21:0612] type 00 class 0x010601
> [    0.574458] pci 0000:01:00.0: BAR 0 [io  0x0000-0x0007]
> [    0.574541] pci 0000:01:00.0: BAR 1 [io  0x0000-0x0003]
> [    0.574616] pci 0000:01:00.0: BAR 2 [io  0x0000-0x0007]
> [    0.574774] pci 0000:01:00.0: BAR 3 [io  0x0000-0x0003]
> [    0.574854] pci 0000:01:00.0: BAR 4 [io  0x0000-0x001f]
> [    0.574925] pci 0000:01:00.0: BAR 5 [mem 0x00000000-0x000001ff]
> [    0.575001] pci 0000:01:00.0: ROM [mem 0x00000000-0x0000ffff pref]
> [    0.575765] pci 0000:01:00.0: 2.000 Gb/s available PCIe bandwidth, limited by
> 2.5 GT/s PCIe x1 link at 0000:00:00.0 (capable of 4.000 Gb/s with 5.0 GT/s PCIe
> x1 link)
> [    0.576808] pci 0000:00:00.0: BAR 0 [mem 0x01000000-0x010fffff]: assigned
> [    0.576860] pci 0000:00:00.0: bridge window [mem 0x01100000-0x011fffff]:
> assigned
> [    0.576895] pci 0000:00:00.0: bridge window [mem 0x01200000-0x012fffff
> pref]: assigned
> [    0.576928] pci 0000:00:00.0: ROM [mem 0x01300000-0x0130ffff pref]:
> assigned
> [    0.576958] pci 0000:00:00.0: bridge window [io  0x1000-0x1fff]: assigned
> [    0.577000] pci 0000:01:00.0: ROM [mem 0x01200000-0x0120ffff pref]:
> assigned
> [    0.577033] pci 0000:01:00.0: BAR 5 [mem 0x01100000-0x011001ff]: assigned
> [    0.577087] pci 0000:01:00.0: BAR 4 [io  0x1000-0x101f]: assigned
> [    0.577212] pci 0000:01:00.0: BAR 0 [io  0x1020-0x1027]: assigned
> [    0.577273] pci 0000:01:00.0: BAR 2 [io  0x1028-0x102f]: assigned
> [    0.577326] pci 0000:01:00.0: BAR 1 [io  0x1030-0x1033]: assigned
> [    0.577377] pci 0000:01:00.0: BAR 3 [io  0x1034-0x1037]: assigned
> [    0.577429] pci 0000:00:00.0: PCI bridge to [bus 01-ff]
> [    0.577460] pci 0000:00:00.0:   bridge window [io  0x1000-0x1fff]
> [    0.577491] pci 0000:00:00.0:   bridge window [mem 0x01100000-0x011fffff]
> [    0.577520] pci 0000:00:00.0:   bridge window [mem 0x01200000-0x012fffff
> pref]
> [    0.579109] pcieport 0000:00:00.0: PME: Signaling with IRQ 291
> [    0.580323] pcieport 0000:00:00.0: AER: enabled with IRQ 291
Hi Leonardo & Francesco:
I looked through the code changes in commit 610fa91d9863 ("PCI: imx6: Assert PERST# before enabling regulators").

I noticed there are changes to the sequence between clk_enable() and
assert_core_reset():

+       ret = imx_pcie_clk_enable(imx_pcie);
+       if (ret) {
+               dev_err(dev, "unable to enable pcie clocks: %d\n", ret);
+               goto err_reg_disable;
+       }
+
        if (pp->bridge && imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_LUT)) {
                pp->bridge->enable_device = imx_pcie_enable_device;
                pp->bridge->disable_device = imx_pcie_disable_device;
        }

        imx_pcie_assert_core_reset(imx_pcie);
-       imx_pcie_assert_perst(imx_pcie, true);

        if (imx_pcie->drvdata->init_phy)
                imx_pcie->drvdata->init_phy(imx_pcie);

        imx_pcie_configure_type(imx_pcie);

-       ret = imx_pcie_clk_enable(imx_pcie);
-       if (ret) {
-               dev_err(dev, "unable to enable pcie clocks: %d\n", ret);
-               goto err_reg_disable;
-       }
-

Based on v7.2-rc7, can you help to verify the new sequence below can resolve your problem or not?

diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index f7389b5437dfe..f799e4b62815a 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -1388,12 +1388,6 @@ static int imx_pcie_host_init(struct dw_pcie_rp *pp)
                goto err_pwrctrl_destroy;
        }

-       ret = imx_pcie_clk_enable(imx_pcie);
-       if (ret) {
-               dev_err(dev, "unable to enable pcie clocks: %d\n", ret);
-               goto err_pwrctrl_power_off;
-       }
-
        if (pp->bridge && imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_LUT)) {
                pp->bridge->enable_device = imx_pcie_enable_device;
                pp->bridge->disable_device = imx_pcie_disable_device; @@ -1409,6 +1403,12 @@ static int imx_pcie_host_init(struct dw_pcie_rp *pp)

        imx_pcie_configure_type(imx_pcie);

+       ret = imx_pcie_clk_enable(imx_pcie);
+       if (ret) {
+               dev_err(dev, "unable to enable pcie clocks: %d\n", ret);
+               goto err_pwrctrl_power_off;
+       }
+
        if (imx_pcie->phy) {
                ret = phy_init(imx_pcie->phy);
                if (ret) {

Best Regards
Richard Zhu