[PATCH] arm64: dts: imx95-15x15-frdm: add boot phase properties

Add boot phase properties to essential resources during boot phase.

FRDM-IMX95 need UART, SD-Card, eMMC access during boot process.

Signed-off-by: Joseph Guo <[email protected]>
---
 arch/arm64/boot/dts/freescale/imx95-15x15-frdm.dts | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx95-15x15-frdm.dts b/arch/arm64/boot/dts/freescale/imx95-15x15-frdm.dts
index 0f43e3be70589532763f65f1699f31dd361cc841..ba17d87f197a3d3498a815fb82547bd810b3e57d 100644
--- a/arch/arm64/boot/dts/freescale/imx95-15x15-frdm.dts
+++ b/arch/arm64/boot/dts/freescale/imx95-15x15-frdm.dts
@@ -140,6 +140,7 @@ reg_usdhc2_vmmc: regulator-usdhc2 {
 		regulator-name = "VDD_SD2_3V3";
 		gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
 		enable-active-high;
+		bootph-pre-ram;
 	};
 
 	reg_usdhc3_vmmc: regulator-usdhc3 {
@@ -445,6 +446,7 @@ led_backlight1: led@1 {
 &lpuart1 {
 	pinctrl-0 = <&pinctrl_uart1>;
 	pinctrl-names = "default";
+	bootph-pre-ram;
 	status = "okay";
 };
 
@@ -721,6 +723,7 @@ pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
 		fsl,pins = <
 			IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7			0x31e
 		>;
+		bootph-pre-ram;
 	};
 
 	pinctrl_uart1: uart1grp {
@@ -728,6 +731,7 @@ pinctrl_uart1: uart1grp {
 			IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX		0x31e
 			IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX		0x31e
 		>;
+		bootph-pre-ram;
 	};
 
 	pinctrl_uart5: uart5grp {
@@ -753,6 +757,7 @@ IMX95_PAD_SD1_DATA6__USDHC1_DATA6			0x138e
 			IMX95_PAD_SD1_DATA7__USDHC1_DATA7			0x138e
 			IMX95_PAD_SD1_STROBE__USDHC1_STROBE			0x158e
 		>;
+		bootph-pre-ram;
 	};
 
 	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
@@ -769,6 +774,7 @@ IMX95_PAD_SD1_DATA6__USDHC1_DATA6			0x138e
 			IMX95_PAD_SD1_DATA7__USDHC1_DATA7			0x138e
 			IMX95_PAD_SD1_STROBE__USDHC1_STROBE			0x158e
 		>;
+		bootph-pre-ram;
 	};
 
 	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
@@ -785,12 +791,14 @@ IMX95_PAD_SD1_DATA6__USDHC1_DATA6			0x13fe
 			IMX95_PAD_SD1_DATA7__USDHC1_DATA7			0x13fe
 			IMX95_PAD_SD1_STROBE__USDHC1_STROBE			0x15fe
 		>;
+		bootph-pre-ram;
 	};
 
 	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
 		fsl,pins = <
 			IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0			0x31e
 		>;
+		bootph-pre-ram;
 	};
 
 	pinctrl_usdhc2: usdhc2grp {
@@ -803,6 +811,7 @@ IMX95_PAD_SD2_DATA2__USDHC2_DATA2			0x138e
 			IMX95_PAD_SD2_DATA3__USDHC2_DATA3			0x138e
 			IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT			0x51e
 		>;
+		bootph-pre-ram;
 	};
 
 	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
@@ -815,6 +824,7 @@ IMX95_PAD_SD2_DATA2__USDHC2_DATA2			0x138e
 			IMX95_PAD_SD2_DATA3__USDHC2_DATA3			0x138e
 			IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT			0x51e
 		>;
+		bootph-pre-ram;
 	};
 
 	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
@@ -827,6 +837,7 @@ IMX95_PAD_SD2_DATA2__USDHC2_DATA2			0x138e
 			IMX95_PAD_SD2_DATA3__USDHC2_DATA3			0x138e
 			IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT			0x51e
 		>;
+		bootph-pre-ram;
 	};
 
 	pinctrl_usdhc3: usdhc3grp {
@@ -1001,6 +1012,7 @@ &usdhc1 {
 	pinctrl-3 = <&pinctrl_usdhc1>;
 	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
 	fsl,tuning-step = <1>;
+	bootph-pre-ram;
 	status = "okay";
 };
 
@@ -1014,6 +1026,7 @@ &usdhc2 {
 	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
 	vmmc-supply = <&reg_usdhc2_vmmc>;
 	fsl,tuning-step = <1>;
+	bootph-pre-ram;
 	status = "okay";
 };
 

---
base-commit: eba4724641990bd9975ca10ababe726b6143f0b6
change-id: 20260814-bootph-frdm-imx95-a4124d7bede4

Best regards,
-- 
Joseph Guo <[email protected]>