Re: [PATCH v38 6/7] arm64: dts: imx8ulp: add secure enclave node

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] The patch explicitly mentions that boards enable the enclave by including 'imx8ulp-firmware.dtsi', but this file is missing from the patch series.
- [Low] The disabled 'hsm0' node lacks the 'memory-region' property, causing an unconditional device tree schema validation warning.
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--- Patch [6]: [PATCH v38 6/7] arm64: dts: imx8ulp: add secure enclave node ---
commit 031e0af8a8a7b64a1399f13195904638982a6007
Author: Pankaj Gupta <[email protected]>

arm64: dts: imx8ulp: add secure enclave node

Add the EdgeLock Enclave (ELE) secure-enclave node to the i.MX8ULP SoC dtsi.

> Keep the node disabled in the SoC dtsi so it does not impose a
> reserved-memory requirement on every board. Boards enable the enclave and
> provide its memory-region by including imx8ulp-firmware.dtsi.

[Severity: Medium]
The commit message mentions that boards enable the enclave by including
imx8ulp-firmware.dtsi, but this file appears to be missing from the patch.
Did you intend to include it in this series?

> diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
> index c6d1bb9edf388..38233dd74ee33 100644
> --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi

[ ... ]

> @@ -185,6 +185,14 @@ scmi_sensor: protocol@15 {
>  				#thermal-sensor-cells = <1>;
>  			};
>  		};
> +
> +		hsm0: secure-enclave {
> +			compatible = "fsl,imx8ulp-se-ele-hsm";
> +			mbox-names = "tx", "rx";
> +			mboxes = <&s4muap 0 0>, <&s4muap 1 0>;
> +			sram = <&sram0>;
> +			status = "disabled";
> +		};
>  	};

[Severity: Low]
Does omitting the memory-region property here cause dtbs_check validation
warnings?

Even when the node is disabled, the fsl,imx-se.yaml binding schema might
unconditionally require the memory-region property for fsl,imx8ulp-se-ele-hsm.

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Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=6