Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The commit message incorrectly claims to modify the CPU address instead of the PCIe bus address.
--
--- Patch [3]: [PATCH v1 3/3] arm64: dts: imx943: Avoid 32-bit PCIe window System RAM overlap ---
commit 06a8fbf859a9df88332de43a908bb91e8293759a
Author: Richard Zhu <[email protected]>
arm64: dts: imx943: Avoid 32-bit PCIe window System RAM overlap
This commit updates the PCIe non-prefetchable memory range for the imx943 to
avoid overlapping with DRAM. It adjusts the outbound address space
configuration to use a safe, reserved range.
> diff --git a/arch/arm64/boot/dts/freescale/imx943.dtsi b/arch/arm64/boot/dts/freescale/imx943.dtsi
> --- a/arch/arm64/boot/dts/freescale/imx943.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx943.dtsi
[ ... ]
> @@ -219,7 +219,7 @@ pcie1: pcie@4c380000 {
> <0 0x4c3c0000 0 0x4000>;
> reg-names = "dbi", "config", "atu", "app";
> ranges = <0x43000000 0xa 0x00000000 0xa 0x00000000 0x0 0xe0000000>,
> - <0x82000000 0x0 0xe0000000 0xa 0xe0000000 0x0 0x10000000>,
> + <0x82000000 0x0 0x10000000 0xa 0xe0000000 0x0 0x10000000>,
[Severity: Medium]
The commit message states that this moves the PCIe non-prefetchable memory
CPU address from 0xe0000000 to 0x10000000. Is this description accurate?
Looking at the ranges property in pcie1, the format is
<child_hi child_mid child_low parent_hi parent_low size_hi size_low>.
This change modifies the third cell (child_low), which represents the PCIe
bus address, from 0xe0000000 to 0x10000000. However, the fourth and fifth
cells representing the parent CPU address remain completely unchanged at
0xa 0xe0000000.
Does the code need to change the parent CPU address cells instead, or should
the commit message be updated to reflect that the child bus address is what
is actually being modified?
> <0x81000000 0x0 0x00000000 0xa 0xf0000000 0x0 0x00100000>;
> #address-cells = <3>;
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Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=3
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