Re: [PATCH v5 36/49] Documentation: KVM: Document KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS for VGICv5

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Restricting user-space writes to VGICv5 system registers, IRS MMIO registers, and IST state after a VCPU has run prevents VM soft reset.
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--- Patch [36]: [PATCH v5 36/49] Documentation: KVM: Document KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS for VGICv5 ---
commit 5be826b5b86ddbcfa778f582ad314ba1e4599113
Author: Sascha Bischoff <[email protected]>

Documentation: KVM: Document KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS for VGICv5
    
This commit documents the KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS API for the virtual
GICv5, defining the register layout, supported system registers, and error
codes.

> diff --git a/Documentation/virt/kvm/devices/arm-vgic-v5.rst b/Documentation/virt/kvm/devices/arm-vgic-v5.rst
> index c782ea4d4609c..7e41d6699538f 100644
> --- a/Documentation/virt/kvm/devices/arm-vgic-v5.rst
> +++ b/Documentation/virt/kvm/devices/arm-vgic-v5.rst
[ ... ]
> +  Errors:
> +
> +    =======  =============================================================
> +    -ENXIO   Getting or setting this register is not supported
> +    -EBUSY   VCPU is running, or write attempted after a VCPU has run

[Severity: High]
Does returning -EBUSY when a write is attempted after a VCPU has run prevent
VM soft resets?

During a soft reset (such as PSCI SYSTEM_RESET), QEMU typically pauses the
vCPUs and rewrites the initial state of the GIC device while the KVM VM is
still considered to have run once, since it doesn't destroy and recreate the
entire KVM VM.

If KVM enforces this restriction on KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS and
other device states, won't this reject QEMU's state restore sequence and
prevent the VM from rebooting gracefully?

> +    -EINVAL  Invalid mpidr or register value supplied
> +    =======  =============================================================

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Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=36