[PATCH 0/5] arm64: gic-v5: Fixes from GICv5 KVM IRS review

Hi all,

While reviewing v4 of the KVM GICv5 IRS series [1], Sashiko [2]
identified a number of issues in GICv5 and vGIC code that has already
been merged. This series contains the fixes for these issues.

The fixes are:

* Free gic_kvm_info when vGIC initialisation fails because the
  maintenance interrupt is not provided but is required. This routes
  the failure through the existing cleanup path to free gic_kvm_info
  again.

* Clear the per-CPU IRS pointer and IAFFID state when host IRS
  initialisation fails or an IRS is removed. This prevents the per-CPU
  state from retaining a pointer to freed IRS data, thereby avoiding a
  potential deference of a stale pointer later on.

* Add an isb() after disabling the GICv5 CPU interface. This ensures
  that interrupts are disabled before the helper returns.

* Fix speculative accesses in the common vGIC SPI lookup which could
  previously underflow. The SPI index is now made relative to the SPI
  array before array_index_nospec() constrains it rather than
  afterwards.

* Reject GICv5 PPIs outside KVM's supported private IRQ range. These
  were previously clamped to zero, and hence would alias private IRQ 0
  for an out-of-range PPI ID.

These changes are based on v7.2-rc7.

Thanks,
Sascha

[1] https://lore.kernel.org/all/[email protected]/
[2] https://sashiko.dev/#/patchset/20260724104819.1296803-1-sascha.bischoff%40arm.com

Sascha Bischoff (5):
  KVM: arm64: vgic: Free gic_kvm_info on initialization failure
  irqchip/gic-v5: Clear per-CPU IRS data on teardown
  irqchip/gic-v5: Synchronize CPU interface disable
  KVM: arm64: vgic: Prevent speculative SPI array underflow
  KVM: arm64: vgic: Reject out-of-range GICv5 PPI IDs

 arch/arm64/kvm/vgic/vgic-init.c  |  4 +++-
 arch/arm64/kvm/vgic/vgic.c       |  7 +++++--
 drivers/irqchip/irq-gic-v5-irs.c | 16 ++++++++++++++++
 drivers/irqchip/irq-gic-v5.c     |  1 +
 4 files changed, 25 insertions(+), 3 deletions(-)

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2.34.1