Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
Pre-existing issues:
- [High] Helper functions for fault status codes do not check for level -2 page table faults, despite the underlying macros explicitly supporting them.
--
--- Patch [13]: [PATCH v19 13/14] tools: Synchronise the kernel esr.h ---
commit 5fb6f6b253d11f55810a8290d81373d977245cee
Author: Mark Brown <[email protected]>
tools: Synchronise the kernel esr.h
This commit synchronizes the tools version of the arm64 esr.h header with
the main kernel header. It primarily picks up new definitions for GCS
(Guarded Control Stack) alongside other fault status helpers.
> diff --git a/tools/arch/arm64/include/asm/esr.h b/tools/arch/arm64/include/asm/esr.h
> index f3c6403e5ef2b..24c6ebe3fd416 100644
> --- a/tools/arch/arm64/include/asm/esr.h
> +++ b/tools/arch/arm64/include/asm/esr.h
[ ... ]
> @@ -439,6 +490,46 @@ static inline bool esr_fsc_is_access_flag_fault(unsigned long esr)
[ ... ]
> +static inline bool esr_fsc_is_addr_sz_fault(unsigned long esr)
> +{
> + esr &= ESR_ELx_FSC;
> +
> + return (esr == ESR_ELx_FSC_ADDRSZ_L(3)) ||
> + (esr == ESR_ELx_FSC_ADDRSZ_L(2)) ||
> + (esr == ESR_ELx_FSC_ADDRSZ_L(1)) ||
> + (esr == ESR_ELx_FSC_ADDRSZ_L(0)) ||
> + (esr == ESR_ELx_FSC_ADDRSZ_L(-1));
> +}
[Severity: High]
This is a pre-existing issue, but does this helper (along with the existing
esr_fsc_is_translation_fault() function) fail to check for level -2 page
table faults?
If a guest VM utilizing 128-bit page tables (FEAT_D128) encounters a stage-2
translation fault at level -2 (FSC 0x2A) or an address size fault (FSC 0x2C),
would KVM's MMU exit handler fail to recognize the fault because the -2 level
is omitted here?
It looks like missing the (esr == ESR_ELx_FSC_ADDRSZ_L(-2)) and the
corresponding ESR_ELx_FSC_FAULT_L(-2) check might cause the host to treat a
legitimate memory access as an unhandled abort, resulting in a VM crash.
--
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=13
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