Re: [PATCH] arm64: dts: allwinner: a523: x96qpro+: overvolting eMMC

On Mon, 20 Jul 2026 21:50:35 +0000
[email protected] wrote:

> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> - [High] Bumping the eMMC IO regulator (`reg_cldo1`) to 1.9V inadvertently misconfigures the SoC's IO bank (Port C) into 3.3V power mode instead of 1.8V mode, creating a logic threshold mismatch.

Huh, that's interesting, but might actually point to the real root
cause: it seems like the meaning of the bits in the withstand register
is inverted on the A523: 0 encodes 1.8V, a 1 encodes 3.3V. But that's
the opposite of the H6 definition, which we use in the kernel for the
A523 as well. Which means they were wrongly programmed before, but now
the wrong voltage selection turns out to trigger the really correct
setting.

So I will try playing around with those registers instead.

Cheers,
Andre.


> --
> 
> --- Patch [1]: [PATCH] arm64: dts: allwinner: a523: x96qpro+: overvolting eMMC ---
> commit e4c261c388d6e406babdf0d56ac61d104d537230
> Author: Andre Przywara <[email protected]>
> Date:   Mon Jul 20 21:38:32 2026 +0000
> 
> arm64: dts: allwinner: a523: x96qpro+: overvolting eMMC
> 
> This commit changes the eMMC IO regulator voltage on PortC from 1.8V to 1.9V
> for the X96QPro+ device. The goal is to improve eMMC stability and performance
> without drastically limiting the clock frequency.
> 
> > diff --git a/arch/arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dts b/arch/arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dts
> > --- a/arch/arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dts
> > +++ b/arch/arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dts
> [ ... ]
> > @@ -194,8 +194,8 @@ reg_bldo4: bldo4 {
> >  
> >  			reg_cldo1: cldo1 {
> >  				regulator-always-on;
> > -				regulator-min-microvolt = <1800000>;
> > -				regulator-max-microvolt = <1800000>;
> > +				regulator-min-microvolt = <1900000>;
> > +				regulator-max-microvolt = <1900000>;
> 
> [Severity: High]
> Does bumping this regulator to 1.9V inadvertently force the SoC's IO bank
> (Port C) into 3.3V power mode?
> 
> Looking at sunxi_pinctrl_set_io_bias_cfg() in
> drivers/pinctrl/sunxi/pinctrl-sunxi.c, the driver uses a strict check when
> evaluating the voltage:
> 
>     case BIAS_VOLTAGE_PIO_POW_MODE_SEL:
>         val = uV <= 1800000 ? 1 : 0;
> 
> Since 1900000 is greater than 1800000, this evaluates to 0 and clears the
> PIO_POW_MOD_SEL register bit, incorrectly configuring the IO bank for 3.3V
> mode while being powered at 1.9V.
> 
> Could this mismatch alter input receiver thresholds and drive strengths,
> potentially causing signal integrity issues or long-term hardware
> degradation?
> 
> >  				regulator-name = "vcc-codec-sd";
> >  			};
>